Semiconductor device including multiple field effect transistors, with first fets having oxide spacers and the second fets having oxide nitride oxidation protection

ABSTRACT

A semiconductor device and a manufacturing method thereof permitting the quality of gate insulating films to be prevented from deteriorating and thereby permitting electrical characteristics of the device to be prevented from deteriorating are provided. In a semiconductor device including a plurality of field effect transistors, an oxidation protection film  21  is formed on a side of one gate electrode  19.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to semiconductor devices andmanufacturing methods thereof, and more particularly, to a semiconductordevice including a plurality of field effect transistors and amanufacturing method thereof.

2. Description of the Background Art

In recent years, as semiconductor devices came to be more denselyintegrated and reduced in size, 2-power supply devices having externalvoltage of a conventional level and internal voltage of a lower levelhave been proposed.

FIG. 79 is a cross sectional view showing such a conventional 2-powersupply semiconductor device including a plurality of field effecttransistors.

Referring to FIG. 79, the conventional 2-power supply semiconductordevice include a first field effect transistor supplied with first powersupply voltage (low Vdd) and a second field effect transistor suppliedwith second power supply voltage (high Vdd) higher than low Vdd formedon a main surface of a p type semiconductor substrate 101 and spacedapart from each other. An isolation oxide film 102 is formed between thefirst and second field effect transistors.

In the low Vdd region, a pair of first source/drain regions 110 and apair of low concentration impurity diffusion regions 108 are formedspaced apart from each other on the main surface of semiconductorsubstrate 101 having a first channel region therebetween. Lowconcentration, n type impurity diffusion region 108 formed adjacent tothe first channel region and high concentration, n type impuritydiffusion region 110 formed adjacent to n type impurity diffusion region108 constitute an LDD (Lightly Doped Drain) structure. A first gateinsulating film 106 is formed on the first channel region. A first gateelectrode 118 is formed on first gate insulating film 106. A sidewalloxide film 109 is formed on a side of first gate electrode 118. Thefirst field effect transistor supplied with low Vdd is formed of firstsource/drain regions 110, impurity diffusion regions 108, first gateinsulating film 106, and first gate electrode 118.

In the high Vdd region, a pair of second source/drain regions 117 and apair of low concentration impurity diffusion regions 116 are formed onthe main surface of semiconductor substrate 101, spaced apart from eachother and having a second channel region therebetween. Secondsource/drain region 117 and low concentration impurity diffusion region116, in other words low concentration n type impurity diffusion region116 formed adjacent to the second channel region and high concentration,n type impurity diffusion region 117 formed adjacent to n type impuritydiffusion region 116 constitute an LDD structure. A second gateinsulating film 104 is formed on the second channel region. First gateinsulating film 106 is formed on second gate insulating film 104. Asecond gate electrode 119 is formed on first gate insulating film 106. Asidewall oxide film 120 is formed on a side of second gate electrode119. Second source/drain regions 117 and impurity diffusion region 116,second gate insulating film 104, first gate insulating film 106 andfirst gate electrode 119 form the second field effect transistorsupplied with high Vdd. The gate insulating films 104 and 106 of thesecond field effect transistor supplied with high Vdd should be thickerthan the first gate insulating film 106 of first field effect transistorsupplied with low Vdd.

Referring to FIGS. 80 to 86, a method of manufacturing the conventional2-power supply semiconductor device will be now described.

Isolation oxide film 102 is formed on the main surface of semiconductorsubstrate 101 to surround an active region. Second gate insulating film104 is formed on the active region on the main surface of semiconductorsubstrate 101. A resist pattern 105 a is formed on second gateinsulating film 104 positioned in the high Vdd region and on isolationoxide film 102. The structure as shown in FIG. 80 is thus obtained.

An isotropic etching is performed using resist pattern 105 a as a maskto remove second gate insulating film 104 positioned in the low Vddregion to obtain the structure as shown in FIG. 81. Resist pattern 105 ais then removed.

As shown in FIG. 82, first gate insulating film 106 is formed on themain surface of semiconductor substrate 101 and on second gateinsulating film 104.

A first doped polysilicon film 103 (see FIG. 83) is deposited on firstgate insulating film 106 and isolation oxide film 102. Resist patterns105 b and 105 c are formed on the regions of first doped polysiliconfilm 103 to be first and second gate electrodes 118 and 119 (see FIG.79). The structure as shown in FIG. 83 is thus obtained.

Then, using resist patterns 105 b and 105 c as masks, an anisotropicetching is performed to remove a part of first doped polysilicon film103, and first and second gate electrodes 118 and 119 are formed as aresult. Resist patterns 105 b and 105 c are then removed. The structureas shown in FIG. 84 is thus obtained. The gate insulating film portionof the second field effect transistor formed of first and second gateinsulating films 106 and 104 can be made thicker than the first gateinsulating film 106 of the first field effect transistor. Thus, thebreakdown voltage of the second field effect transistor can be greaterthan the breakdown voltage of the first field effect transistor, so thatthe second field effect transistor may be supplied with voltage higherthan the first field effect transistor.

As shown in FIG. 85, an n type impurity is introduced into a prescribedregion of the main surface of semiconductor substrate 101 to form lowconcentration n type impurity diffusion regions 108 and 116.

Sidewall oxide films 109 and 120 (see FIG. 86) are formed on sides offirst and second gate electrodes 118 and 119. An n type impurity is thenintroduced into a prescribed region of the main surface of semiconductorsubstrate 101 to form high concentration n type impurity diffusionregions 110 and 117 as shown in FIG. 86.

The conventional 2-power supply semiconductor device is manufactured asdescribed above.

In the manufacture of the 2-power supply semiconductor device, resistpattern 105 a is directly formed on second gate insulating film 104positioned in the high Vdd region. In the following removal of resistpattern 105 a, defects (local irregularities) are sometimes generated inthe surface of second gate insulating film 104. A light etchingprocessing for removing resist pattern 105 a is directly performed tothe surface of second gate insulating film 104, second gate insulatingfilm 104 may be reduced in thickness. The defects in the surface ofsecond gate insulating film 104 and the reduction in thickness lead to areduction in the breakdown voltage of second gate insulating film 104,and as a result electrical characteristics of the semiconductor deviceincluding the field effect transistor deteriorate.

As a countermeasure, a manufacturing method as shown in FIGS. 87 to 93has been proposed.

Referring to FIGS. 87 to 93, the proposed conventional method ofmanufacturing a 2-power supply semiconductor device including aplurality of field effect transistors will be described.

Isolation oxide film 102 is formed on the main surface of p typesemiconductor substrate 101 to surround an active region. Second gateinsulating film 104 is formed on the active region in the main surfaceof p type semiconductor substrate 101. First doped polysilicon film 103is formed on second gate insulating film 104 and isolation oxide film102. Resist pattern 105 a is formed on the region of first dopedpolysilicon film 103 to be second gate electrode 119 (see FIG. 88)positioned in the high Vdd region to obtain the structure as shown inFIG. 87.

An anisotropic etching is performed using resist pattern 105 a as a maskto etch away a part of first doped polysilicon film 103, and second gateelectrode 119 as shown in FIG. 88 results. Resist pattern 105 a is thenremoved. Resist pattern 105 b is formed on second gate insulating film104 positioned in the high Vdd region and second gate electrode 119 toform the structure as shown in FIG. 88.

In the manufacture, second gate electrode 119 is formed on second gateinsulating film 104 and then resist pattern 105 b is formed. Resistpattern 105 b is not directly formed on the region of the surface ofsecond gate insulating film 104 in contact with second gate electrode119. Thus, defects in the surface of second gate insulating film 104 asin the manufacturing method shown in FIGS. 80 to 86 can be prevented.

Then, as shown in FIG. 89, second gate insulating film 104 positioned inthe low Vdd region is removed by an isotropic etching. Then, resistpattern 105 b is removed.

As shown in FIG. 90, a silicon oxide film to be first gate insulatingfilm 106 is formed on the main surface of p type semiconductor substrate101 positioned in the low Vdd region and on second gate insulating film104 and second gate electrode 119.

Then, on first gate insulating film 106 and isolation oxide film 102, asecond doped polysilicon film 107 (see FIG. 91) is formed by means ofCVD. Resist pattern 105 c (see FIG. 91) is formed on the region ofsecond doped polysilicon film 107 to be first gate electrode 118 (seeFIG. 93). The structure as shown in FIG. 91 is thus obtained.

An anisotropic etching is performed using resist pattern 105 c as a maskto remove a part of second doped polysilicon film 107, and first gateelectrode 118 (see FIG. 92) is formed as a result. After the anisotropicetching, a part of second doped polysilicon film 107 also remains on aside of second gate electrode 119. Resist pattern 105 c is then removed.Resist pattern 105 d (see FIG. 92) is formed on first gate insulatingfilm 106 positioned in the low Vdd region and on first gate electrode118. Thus, the structure as shown in FIG. 92 results.

Second doped polysilicon film 107 remaining on the side of second gateelectrode is removed by an isotropic etching, and then resist pattern105 d is removed. After low concentration, n type impurity diffusionregions 108, 116 (see FIG. 93) are formed by introducing an impurity,sidewall oxide films 109, 120 (see FIG. 93) are formed, followed byformation of high concentration n type impurity diffusion regions 110,117 (see FIG. 93), and the semiconductor device as shown in FIG. 93results.

In the manufacture of the proposed conventional 2-power supplysemiconductor device as shown in FIGS. 87 to 93, second gate electrode119 is formed before resist pattern 105 b is formed as shown in FIG. 88,in order to prevent defects from being formed in the surface of secondgate insulating film 104. In the manufacture of the 2-power supplysemiconductor device, however, in the step as shown in FIG. 90, duringforming first gate insulating film 106, second gate electrode 119 formedof doped polysilicon is oxidized in an end 123 of the contact portionbetween second gate electrode 119 and second gate insulating film 104 asshown in FIG. 94. Therefore, a silicon oxide film 124 grows along thecontact surface between second gate insulating film 104 and second gateelectrode 119. Thus grown silicon oxide film is called “gate bird'sbeak”. Herein, FIG. 94 is an enlarged view of region 110 shown in FIG.90. The gate oxide film having a “gate bird's beak” formed of an oxidefilm is poor in quality and difficult to control in thickness. As aresult, electrical characteristics of the semiconductor device includingthe plurality of field effect transistors deteriorate.

SUMMARY OF THE INVENTION

The present invention is directed to a solution to the above-describedproblems. It is one object of the invention to provide a semiconductordevice which can prevent electrical characteristics of the device fromdeteriorating by preventing the deterioration of the quality of a gateinsulating film.

Another object of the invention is to provide a semiconductor devicewhich can prevent a gate bird's beak from being generated.

Yet another object of the invention is to provide a method ofmanufacturing a semiconductor device which can prevent the deteriorationof the quality of a gate insulating film.

A semiconductor device according to one aspect of the invention having aplurality of field effect transistors includes first and second fieldeffect transistors.

The first field effect transistor includes a pair of first source/drainregions, a first gate insulating film, and a first gate electrode. Thesecond field effect transistor includes a pair of second source/drainregions, a second gate insulating film, and a second gate electrode. Thefirst source/drain regions are formed, on a main surface of asemiconductor substrate, spaced apart from each other and having a firstchannel region therebetween. The first gate insulating film is formed onthe first channel region in a first thickness. The second source/drainregions are formed on the main surface of the semiconductor substrate,spaced apart from each other and having a second channel regiontherebetween. The second gate insulating film is formed on the secondchannel region in a second thickness larger than the first thickness.The second gate electrode is formed on the second gate insulating film.An oxidation protection film to prevent one of the first and second gateelectrodes from being oxidized is formed on a side of one of the gateelectrodes. In the semiconductor device according to this aspect, theoxidation protection film to prevent the gate electrode from beingoxidized is formed on a side of one of the first and second gateelectrodes, and therefore an oxidizing step to form a gate insulatingfilm of another field effect transistor may be performed while theoxidization protection film is formed on a side of that one gateelectrode. As a result, the lower part of the side of the gate electrodecan be prevented from being oxidized, and a gate bird's beak can beavoided. Thus, the threshold voltages of the field effect transistorscan be prevented from increasing. As a result, electricalcharacteristics of the semiconductor device including the plurality offield effect transistors can be prevented from deteriorating.

A semiconductor device according to another aspect of the inventionhaving a plurality of field effect transistors includes first and secondfield effect transistors.

The first field effect transistor includes a pair of first source/drainregions, a first gate insulating film, and a first gate electrode. Thesecond field effect transistor includes a pair of second source/drainregions, a second gate insulating film, and a second gate electrode. Thefirst source/drain regions are formed, on a main surface of asemiconductor substrate, spaced apart from each other and having a firstchannel region therebetween. The first gate insulating film has a firstthickness and is formed on the first channel region to include an oxidenitride film. The first gate electrode is formed on the first gateinsulating film. The second source/drain regions are formed, on the mainsurface of the semiconductor substrate, spaced apart from each other andhaving a second channel region therebetween. The second gate insulatingfilm is formed on the second channel region and has a second thicknesslarger than the first thickness. The second gate electrode is formed onthe second gate insulating film.

In the semiconductor device according to this aspect, since the firstgate insulating film is formed to include the oxide nitride film, in themanufacturing process which will be described, in the presence of thesecond gate electrode, during forming the oxide nitride film to be thefirst gate insulating film, an end of the second gate electrode can beprevented from being excessively oxidized in the contact portion betweena lower part of a side of the second gate electrode and the second gateinsulating film. Thus, as a result, the lower part of the side of thegate electrode can be prevented from being oxidized, and a gate bird'sbeak can be avoided. Thus, the threshold voltages of the field effecttransistors can be prevented from increasing. As a result, electricalcharacteristics of the semiconductor device including the plurality offield effect transistors can be prevented from deteriorating.Furthermore, since the first gate insulating film is formed to includethe oxide nitride film, the first gate insulating film may be formedthinner with a prescribed breakdown voltage being maintained than thecase of using a conventional silicon oxide film or the like. As aresult, the driving voltage of the first field effect transistor may bereduced.

A semiconductor device according to another aspect of the inventionhaving a plurality of field effect transistors includes first and secondfield effect transistors. The first field effect transistor includes apair of first source/drain regions, a first gate insulating film, and afirst gate electrode. The second field effect transistor includes a pairof second source/drain regions, a second gate insulating film, and asecond gate electrode. The first source/drain regions are formed, on amain surface of a semiconductor substrate, spaced apart from each otherand having a first channel region therebetween. The first gateinsulating film is formed on the first channel region and has a firstthickness. The first gate electrode is formed on the first gateinsulating film. The second source/drain regions are formed, on the mainsurface of the semiconductor substrate, spaced apart from each other andhaving a second channel region therebetween. The gate insulating film isformed on the second channel region and has a second thickness largerthan the first thickness. The second gate electrode is formed on thesecond gate insulating film. An anti-oxidation conductive film is formedon at least one of the first and second gate insulating films.

In the semiconductor device according to this aspect, the anti-oxidationconductive film is formed on at least one of the first and second gateinsulating films, it is not necessary to form a resist pattern directlyon the surface of one of the first and second gate insulating films inthe following manufacturing steps. Furthermore, before forming one ofthe first and second gate electrodes, an oxidizing step to form theother one of the first and second gate insulating films may be performedusing the anti oxidation conductive film. Thus, in the step of oxidizingthe first gate insulating film, a lower part of the side of one of thefirst and second gate electrodes can be prevented from being oxidized,and a gate bird's beak can be avoided. Thus, the threshold voltages ofthe field effect transistors can be prevented from increasing. As aresult, electrical characteristics of the semiconductor device includingthe plurality of field effect transistors can be prevented fromdeteriorating.

Furthermore, since the anti-oxidation conductive film is formed on oneof the first and second gate insulating films, a resist pattern will notbe formed directly on one of the first and second gate insulating filmsin the following manufacturing steps. As a result, defects such as localirregularities in the gate insulating film as formed during removing theresist pattern can be avoided. Therefore, the threshold voltages of thefield effect transistors may be prevented from fluctuating. Electricalcharacteristics of the semiconductor device including the plurality offield effect transistors may be prevented from deteriorating.

In the semiconductor device according to this aspect, a semiconductorfilm having a conductive impurity may be formed at a position betweenthe anti-oxidation conductive film and at least one of the first andsecond gate insulating films.

Thus, when voltage is supplied to one of the first and second gateelectrodes having the semiconductor film including the conductiveimpurity, the formation of a depletion layer caused by a reduction inthe concentration of the conductive impurity in the vicinity of one ofthe first and second gate insulating films may be prevented. As aresult, the fluctuation of the threshold voltages of the field effecttransistors caused by the formation of such a depletion layer can beprevented. Therefore, electrical characteristics of the semiconductordevice including the plurality of field effect transistors can beprevented from deteriorating.

A semiconductor device according to another aspect of the inventionhaving a plurality of field effect transistors includes first and secondfield effect transistors.

The first field effect transistor includes a pair of first source/drainregions, a first gate insulating film, and a first gate electrode. Thesecond field effect transistor includes a pair of second source/drainregions, a second gate insulating film, and a second gate electrode. Thefirst source/drain regions are formed, on a main surface of asemiconductor substrate, spaced apart from each other and having a firstchannel region therebetween. The first gate insulating film is formed onthe first channel region and has a first thickness. The first gateelectrode is formed on the first gate insulating film. The secondsource/drain regions are formed, on the main surface of thesemiconductor substrate, spaced apart from each other and having asecond channel region therebetween. The second gate insulating film isformed on the second channel region and has a second thickness. Thesecond gate electrode is formed on the second gate insulating film. Asemiconductor film having a conductive impurity is formed on and incontact with at least one of the first and second gate insulating films.An anti-oxidation insulating film for preventing the semiconductor filmhaving the conductive impurity from being oxidized is formed on thesemiconductor film.

Since the semiconductor film having the conductive impurity is thusformed on and in contact with one of the first and second gateinsulating films, it is not necessary to form a resist pattern directlyon a surface of one of the first and second gate insulating films in themanufacture of the semiconductor device. Furthermore, before one of thefirst and second gate electrodes is formed, an oxidizing step to formthe other one of the first and second gate insulating films may beperformed using the anti-oxidation insulating film as a mask. In thestep of oxidizing the gate insulating films, a lower part of a side ofthe gate electrodes can be prevented from being oxidized as a result,and a gate bird's beak can be avoided. Thus, the threshold voltages ofthe field effect transistors can be prevented from increasing. As aresult, electrical characteristics of the semiconductor device includingthe plurality of field effect transistors can be prevented fromdeteriorating.

Furthermore, the semiconductor film having the conductive impurity isformed on and in contact with one of the first and second gateinsulating films, a resist pattern is not formed directly on one of thefirst and second gate insulating films. As a result, defects such aslocal irregularities in the gate insulating films as formed duringremoving the resist pattern can be avoided. Therefore, the thresholdvoltages of the field effect transistors may be prevented fromfluctuating. Electrical characteristics of the semiconductor deviceincluding the plurality of field effect transistors may be preventedfrom deteriorating. Furthermore, when voltage is supplied to one of thefirst and second gate electrodes having the semiconductor film includingthe conductive impurity, the formation of a depletion layer caused by areduction in the concentration of the conductive impurity in thevicinity of one of the first and second gate insulating films may beprevented. As a result, the fluctuation of the threshold voltages of thefield effect transistors caused by the formation of such a depletionlayer can be prevented. Therefore, electrical characteristics of thesemiconductor device including the plurality of field effect transistorscan be prevented from deteriorating.

A semiconductor device according to another aspect of the inventionhaving a plurality of field effect transistors includes first and secondfield effect transistors.

The first field effect transistor includes a pair of first source/drainregions, a first gate insulating film, and a first gate electrode. Thesecond field effect transistor includes a pair of second source/drainregions, a second gate insulating film, and a second gate electrode. Thesecond gate electrode has a first conductive film, an insulating filmand a second conductive film. The first source/drain regions are formed,on a main surface of a semiconductor substrate, spaced apart from eachother and having a first channel region therebetween. The first gateinsulating film is formed on the first channel region and has a firstthickness. The first gate electrode is formed on the first gateinsulating film. The second source/drain regions are formed, on the mainsurface of the semiconductor substrate, spaced apart from each other andhaving a second channel region therebetween. The second gate insulatingfilm is formed on the second channel region and has a second thickness.The first conductive film to be a part of the second gate electrode isformed on the second gate insulating film. The insulating film to be apart of the second gate electrode is formed on the first conductivefilm. The second conductive film to be a part of the second gateelectrode is formed on the insulating film.

Thus, the second gate electrode has the first conductive film, theinsulating film, and the second conductive film, and therefore anoxidizing step for forming the first gate insulating film can beperformed before forming the second gate electrode without forming aresist pattern directly on the surface of the second gate insulatingfilm. As a result, a lower part of a side of the gate electrode can beprevented from being oxidized, and a gate bird's beak can be avoided.Thus, the threshold voltages of the field effect transistors can beprevented from increasing. As a result, electrical characteristics ofthe semiconductor device including the plurality of field effecttransistors can be prevented from deteriorating.

A semiconductor device according to another aspect of the inventionhaving a plurality of field effect transistors includes first and secondfield effect transistors.

The first field effect transistor includes a pair of first source/drainregions, a first gate insulating film, and a first gate electrode. Thesecond field effect transistor includes a pair of second source/drainregions, a second gate insulating film, and a second gate electrode. Thefirst source/drain regions are formed, on a main surface of asemiconductor substrate, spaced apart from each other and having a firstchannel region therebetween. The first gate insulating film is formed onthe first channel region and has a first thickness. The first gateelectrode is formed on the first gate insulating film. The secondsource/drain regions are formed, on the main surface of thesemiconductor substrate, spaced apart from each other and having asecond channel region therebetween. The second gate insulating film isformed on the second channel region and has a second thickness largerthan the first thickness. The second gate electrode is formed on thesecond gate insulating film. A protection conductive film is formed onand in contact with at least one of the first and second gate insulatingfilms.

Thus, the protection conductive film is formed on and in, contact withone of the first and second gate insulating films, it is not necessaryto form a resist pattern directly on the surface of one of the first andsecond gate insulating films. Furthermore, before forming one of thefirst and second gate electrodes, an oxidizing step for forming theother one of the first and second gate insulating films can be performedusing the protection conductive film. Thus, in the step of oxidizing thegate insulating films, a lower part of a side of one of the first andsecond gate electrodes can be prevented from being oxidized, and a gatebird's beak can be avoided. Thus, the threshold voltages of the fieldeffect transistors can be prevented from increasing. As a result,electrical characteristics of the semiconductor device including theplurality of field effect transistors can be prevented fromdeteriorating.

In the semiconductor device according to this aspect, the protectionconductive film includes first and second protection conductive films.The first protection conductive film may be formed on and in contactwith the first gate insulating film, while the second protectionconductive film may be formed on and in contact with the second gateinsulating film. The first and second protection conductive films may besubstantially equal in thickness.

Thus, during etching the first and second protection conductive films toform the first and second gate electrodes, the part of the thickness ofthe first and second protection conductive films to be removed by theetching can be made substantially equal in the regions to form the firstand second gate electrodes. As a result, during the etching for formingthe first and second gate electrodes, the amount of etching for formingthe first gate electrode can be substantially the same as the amount ofetching for forming the second gate electrode. Therefore, the amount ofoveretching during forming the first and second gate electrodes can bereduced. As a result, the semiconductor substrate or the like positionedunder the protection conductive films to be etched away can be preventedfrom being damaged by overetching. As a result, electricalcharacteristics of the semiconductor device including the plurality offield effect transistors can be prevented from deteriorating.

The semiconductor device according to this aspect may further include aprotection conductive film formed by depositing a film having anamorphous structure. Thus, the film having the amorphous structure isfree from grain boundaries, and therefore during isotropically etchingthe protection conductive film in the manufacture of the semiconductordevice, damages to the gate insulating film positioned under theprotection conductive film caused by the isotropic etching agent runningalong grain boundaries can be prevented. As a result, the fluctuation ofthe threshold voltages of the field effect transistors can be prevented.As a result, electrical characteristics of the semiconductor deviceincluding the plurality of field effect transistors can be prevented.

In the semiconductor device according to this aspect, an anti-oxidationfilm may be formed on and in contact with the protection conductivefilm. Thus, in the manufacture of the semiconductor device, a naturaloxide film difficult to control in thickness can be prevented from beingformed on the protection conductive film. Thus, in an etching step toform the first and second gate electrodes, the variation of thethickness of the protection conductive film to be etched away caused bythe formation of such a natural oxide film can be prevented. As aresult, during etching for forming the first and second gate electrodes,the variation of the thickness of the protection conductive film to beetched away can be reduced, the amount of overetching, can be reduced.As a result, damages to the semiconductor substrate or the likepositioned under the protection conductive film to be etched away,caused by overetching can be prevented.

In a method of manufacturing a semiconductor device according to anotheraspect of the invention, a first gate insulating film having a firstthickness is formed on a main surface of a semiconductor device. A firstgate electrode is formed on the first gate insulating film. Using thegate electrode as a mask, an impurity is introduced into the mainsurface of the substrate to form a pair of first source/drain regions,spaced apart from each other and having a first channel regiontherebetween. A second gate insulating film having a second thicknesslarger than the first thickness is formed on the main surface of thesemiconductor substrate. Using the second gate electrode as a mask, animpurity is introduced into the main surface of the substrate to form asecond pair of source/drain regions, spaced apart from each other andhaving a second channel region therebetween. An oxidation protectionfilm to prevent a gate electrode from being oxidized is formed on a sideof one of the first and second gate electrodes. After one of the firstand second gate insulating films is formed, the other one of the firstand second gate insulating films is formed with the oxidation protectionfilm being present on the side of the gate electrode formed on that oneof the first and second gate insulating films.

Thus, with the gate electrode being formed on one of the first andsecond gate insulating films, the other one of the first and second gateinsulating films is formed, and therefore resist pattern is not directlyformed on the gate insulating film. Therefore, during the followingremoval of the resist pattern, a direct light etching processing can beprevented on the surface of the gate insulating film. As a result,defects in the surface of the gate insulating film caused by such alight etching processing can be prevented. Furthermore, with theoxidation protection film for preventing a gate electrode from beingoxidized being present on a side of one of the first and second gateelectrodes, an oxidizing step to form the other one of the first andsecond gate insulating films is performed. As a result, a lower part ofa side of the gate electrode can be prevented from being oxidized, and agate bird's beak can be avoided. Thus, the threshold voltages of thefield effect transistors can be prevented from increasing. As a result,electrical characteristics of the semiconductor device including theplurality of field effect transistors can be prevented fromdeteriorating.

In a method of manufacturing a semiconductor device according to anotheraspect of the invention, a first gate insulating film including an oxidenitride film and having a first thickness is formed on a main surface ofa semiconductor substrate. A first gate electrode is formed on the firstgate insulating film. Using the gate electrode as a mask, an impurity isintroduced into the main surface of the substrate to form a pair offirst source/drain regions, spaced apart from each other and having afirst channel region therebetween. A second gate insulating film havinga second thickness larger than the first thickness is formed on the mainsurface of the semiconductor substrate. Using the second gate electrodeas a mask, an impurity is introduced into the main surface of thesubstrate to form a second pair of source/drain regions, spaced apartfrom each other and having a second channel region therebetween. Thefirst gate insulating film is formed in the presence of the second gateelectrode formed on the second gate insulating film.

Thus, while the second gate electrode has been formed on the second gateinsulating film, the first gate insulating film is formed, and thereforeresist pattern is not directly formed on the second gate insulatingfilm. Therefore, during the following removal of the resist pattern, adirect light etching processing on the surface of the second gateinsulating films can be prevented. Thus, defects in the surface of thesecond gate insulating film caused by such a light etching processingcan be prevented.

Furthermore, since there is the step of forming the first gateinsulating film to include the oxide nitride film, an end of the secondgate electrode can be suppressed from being excessively oxidized at thejoint of a lower part of a side of the second gate electrode and thesecond gate insulating film during forming the oxide nitride film to bethe first gate insulating film while the second gate electrode has beenformed. Thus, a gate bird's beak can be avoided. Therefore, thethreshold voltages of the field effect transistors can be preventedincreasing, and as a result electrical characteristics of thesemiconductor device including the plurality of field effect transistorscan be prevented from deteriorating. Since the first gate insulatingfilm is formed to include the oxide nitride film, the thickness of thefirst gate insulating film can be made smaller than the case of using aconventional silicon oxide film as a prescribed breakdown voltage ismaintained. As a result, the driving voltage of the first field effecttransistor can be reduced.

In a method of manufacturing a semiconductor device according to anotheraspect of the invention, a first gate insulating film having a firstthickness is formed on a main surface of a semiconductor substrate. Afirst gate electrode is formed on the first gate insulating film. Usingthe first gate electrode as a mask, an impurity is introduced into themain surface of the substrate to form a pair of first source/drainregions, spaced apart from each other and having a first channel regiontherebetween. A second gate insulating film having a second thicknesslarger than the first thickness is formed on the main surface of thesemiconductor substrate. Using the second gate electrode as a mask, animpurity is introduced into the main surface of the substrate to form asecond pair of source/drain regions, spaced apart from each other andhaving a second channel region therebetween. An anti-oxidationconductive film is formed on at least one of the first and second gateinsulating films. While the anti-oxidation conductive film has beenformed on at least one of the first and second gate insulating films,the other one of the first and second gate insulating films is formed.

Since the anti-oxidation conductive film is formed on one of the firstand second gate insulating films, it is not necessary to directly form aresist pattern on the surface of one of the first and second gateinsulating films. In addition, before forming one of the first andsecond gate electrodes, an oxidizing step to form the other one of thefirst and second gate insulating films can be performed using theanti-oxidation conductive film as a mask. As a result, a lower part of aside of one of the first and second gate electrodes can be preventedfrom being oxidized, and a gate bird's beak can be avoided. Thus, thethreshold voltages of the field effect transistors can be prevented fromincreasing. As a result, electrical characteristics of the semiconductordevice including the plurality of field effect transistors can beprevented from deteriorating.

Furthermore, since the anti-oxidation conductive film is formed on oneof the first and second gate insulating films, a resist pattern is notdirectly formed on that one of the first and second gate insulatingfilms. As a result, defects such as local irregularities in the gateinsulating film as formed during removing a resist pattern can beavoided. Therefore, the threshold voltages of the field effecttransistors may be prevented from fluctuating. Electricalcharacteristics of the semiconductor device including the plurality offield effect transistors may be prevented from deteriorating.

The method of manufacturing the semiconductor device according to thisaspect may further include the step of forming a semiconductor filmincluding a conductive impurity at a position between the anti-oxidationconductive film and at least one of the first and second gate insulatingfilms. Thus, when voltage is supplied to one of the first and secondgate electrodes on the side having the semiconductor film including theconductive impurity, the formation of a depletion layer caused by areduction in the concentration of the conductive impurity in thevicinity of one of the first and second gate insulating films can berestricted. As a result, the fluctuation of the threshold voltages ofthe field effect transistors caused by the formation of such a depletionlayer can be prevented. Therefore, electrical characteristics of thesemiconductor device including the plurality of field effect transistorscan be prevented from deteriorating.

In the method of manufacturing the semiconductor device according tothis aspect, a substrate protection film may be formed in the region onthe main surface of the semiconductor substrate to form one of the firstand second gate insulating films. With the substrate protection filmbeing present, the other one of the first and second gate insulatingfilms and the anti-oxidation conductive film may be formed.

Thus, with the presence of the substrate protection film, the other oneof the first and second gate insulating films and the anti-oxidationconductive film are formed, the insulating film forming the other one ofthe first and second gate insulating film can be prevented from beingformed in contact with the main surface of the semiconductor substratepositioned in the region to form one of the first and second gateinsulating films.

As a result, during etching away the anti-oxidation conductive film andthe insulating film from the region to form one of the first and secondgate insulating films, the main surface of the semiconductor substratepositioned in the region to form that one of the first and second gateinsulating films can be prevented from being directly etched. Thus,damages to the main surface of the semiconductor substrate caused byetching can be prevented. As a result, during forming one of the firstand second gate insulating films, the deterioration of the quality ofone of the first and second gate insulating films caused by the presenceof damages by the etching on the main surface of the semiconductorsubstrate in which the gate insulating film is formed can be prevented.As a result, the fluctuation of the threshold voltage of the fieldeffect transistors can be prevented. As a result, electricalcharacteristics of the semiconductor device including the plurality offield effect transistors can be prevented.

The method of manufacturing the semiconductor device according to thisaspect may further include the step of removing a part of the mainsurface of the semiconductor substrate positioned in the region to formone of the first and second gate insulating films before forming thatinsulating film.

Thus, in the main surface of the semiconductor substrate positioned inthe region to form one of the first and second gate insulating films bymeans of etching in the manufacture of the semiconductor device, a partof the main surface of the semiconductor substrate with damages such aslocal irregularities can be removed. Therefore, that one of the firstand second gate insulating films can be formed on the main surface ofthe semiconductor substrate removed of the damaged part. Therefore, thequality of the gate insulating film can be prevented from deterioratingdue to damages on the main surface of the semiconductor substrate. Thefluctuation of the threshold voltages of the field effect transistorscan be prevented. As a result, electrical characteristics of thesemiconductor device including the plurality of field effect transistorscan be prevented.

In a method of manufacturing a semiconductor device according to anotheraspect of the invention, a first gate insulating film having a firstthickness is formed on a main surface of a semiconductor device. A firstgate electrode is formed on the first gate insulating film. Using thegate electrode as a mask, an impurity is introduced into the mainsurface of the substrate to form a pair of first source/drain regions,spaced apart from each other and having a first channel regiontherebetween. A second gate insulating film having a second thicknesslarger than the first thickness is formed on the main surface of thesemiconductor substrate. A first conductive film to be a part of asecond electrode is formed on the second gate insulating film. Aninsulating film to be a part of the second gate electrode is formed onthe first conductive film. A second conductive film to be a part of thesecond gate electrode is formed on the insulating film. The first andsecond insulating films and the insulating film are anisotropicallyetched to form the second gate electrode. Using the second gateelectrode as a mask, an impurity is introduced into the main surface ofthe substrate to form a second pair of source/drain regions, spacedapart from each other and having a second channel region therebetween.Herein the first gate insulating film is formed in the presence of thefirst conductive film.

Thus, after forming the first conductive film to be a part of the secondgate electrode on the second gate insulating film, the first gateinsulating film is formed, and therefore an oxidizing step to form thefirst gate insulating film can be performed without forming a resistpattern directly on the surface of the second gate insulating film.Therefore, during the following removal of the resist pattern, a directlight etching processing to the surface of the second gate insulatingfilm can be prevented. Thus, defects on the surface of the second gateinsulating film caused by such a light etching processing can beprevented.

In the presence of the first conductive film, after the first gateinsulating film is formed and then the insulating film and the secondconductive films are formed, the first and second conductive films andthe insulating film are anisotropically etched to form the second gateelectrode, a side of the second gate electrode can be prevented frombeing oxidized in the oxidizing step to form the first gate insulatingfilm. Thus, a gate bird's beak can be avoided. Thus, the thresholdvoltages of the field effect transistors can be prevented fromincreasing. As a result, electrical characteristics of the semiconductordevice including the plurality of field effect transistors can beprevented from deteriorating. In the presence of the insulating film,when a voltage is supplied to the second gate electrode, the voltagedrops in the insulating film, and voltage imposed on the second gateinsulating film can be reduced.

In a method of manufacturing a semiconductor device according to anotheraspect of the invention, a first gate insulating film having a firstthickness is formed on a main surface of a semiconductor substrate. Afirst gate electrode is formed on the first gate insulating film. Usingthe gate electrode as a mask, an impurity is introduced into the mainsurface of the substrate to form a pair of first source/drain regions,spaced apart from each other and having a first channel regiontherebetween. A second gate insulating film having a second thicknesslarger than the first thickness is formed on the main surface of thesemiconductor substrate. A second gate electrode is formed on the secondgate insulating film. Using the second gate electrode as a mask, animpurity is introduced into the main surface of the substrate to form apair of second source/drain regions, spaced apart from each other andhaving a second channel region therebetween. A protection conductivefilm for protecting a gate insulating film is formed on and in contactwith at least one of the first and second gate insulating films. Whilethe protection conductive film has been formed, the other one of thefirst and second gate insulating films is formed.

Thus, the protection conductive film is formed on and in contact withone of the first and second gate insulating films, it is not necessaryto directly form a resist pattern on that one of the first and secondgate insulating films. Furthermore, before forming one of the first andsecond gate electrodes, an oxidizing step to form the other one of thefirst and second gate insulating films using the protection conductivefilm as a mask can be performed. As a result, a lower part of the sideof one of the first and second gate electrodes can be prevented frombeing oxidized, and a gate bird's beak can be avoided. Thus, thethreshold voltages of the field effect transistors can be prevented fromincreasing. As a result, electrical characteristics of the semiconductordevice including the plurality of field effect transistors can beprevented from deteriorating.

In the method of manufacturing the semiconductor device according tothis aspect, a conductive film may be formed on and in contact with theother one of the first and second gate insulating films. A resistpattern may be formed on and in contact with the conductive film and theprotection conductive film. Using the resist pattern as a mask, part ofthe conductive film and the protection conductive film isanisotropically etched away to simultaneously form the first gateelectrode and the second gate electrode.

Thus, the resist pattern is formed on and in contact with the protectionconductive film and the conductive film, part of the conductive film andthe protection conductive film is anisotropically etched away using theresist pattern as a mask, and therefore the first and second gateelectrodes can be formed only of the conductive film and the protectionconductive film. As a result, it is not necessary to further form aconductive film to be a part of the gate electrode on the protectionconductive film, the process of manufacturing the semiconductor devicecan be simplified.

In a method of manufacturing a semiconductor device according to anotheraspect of the invention, an insulating film is formed on a main surfaceof a semiconductor substrate positioned in regions to form first andsecond field effect transistors. A resist pattern is formed on theinsulating film positioned in the regions to form the second fieldeffect transistor. Using the resist pattern as a mask, a part of theinsulating film positioned in the region to form the first field effecttransistor is isotropically etched away, followed by removal of theresist pattern. Thus a part of the surface of the insulating film isisotropically etched away to form first and second gate insulatingfilms. A first gate electrode is formed on the first gate insulatingfilm. Using the first gate electrode as a mask, an impurity isintroduced into the main surface of the semiconductor substrate to forma pair of source/drain regions, spaced apart from each other and havinga first channel region therebetween. A second gate electrode is formedon the second gate insulating film. Using the second gate electrode as amask, an impurity is introduced into the main surface of thesemiconductor substrate, to form a pair of second source/drain regions,spaced apart from each other and having a second channel regiontherebetween.

Thus, the first and second gate insulating films are formed of a singleinsulating film, only a single oxidizing step is necessary to form thefirst and second gate insulating films. Since the first and second gateelectrodes are formed after forming the first and second gate insulatingfilms, thus first and second gate electrodes are not oxidized duringforming the first and second gate insulating films. As a result, a lowerpart of a side of the first and second gate electrodes can be preventedfrom being oxidized, and a gate bird's beak can be avoided. Thus, thethreshold voltages of the field effect transistors can be prevented fromincreasing. As a result, electrical characteristics of the semiconductordevice including the plurality of field effect transistors can beprevented from deteriorating.

Furthermore, since only a single oxidizing step is necessary to form thefirst and second gate insulating films, in other words the number ofoxidizing steps to form insulating films is reduced by one as comparedto the conventional method, the process of manufacturing thesemiconductor device can be simplified.

Furthermore, the first and second gate insulating films are formed bymeans of isotropic etching, possible defects such as localirregularities caused by for example a step of ashing during removal ofthe resist pattern on the insulating film to be the first and secondgate insulating films can be removed by the anisotropic etching. As aresult, a defectless, highly reliable gate insulating film may beobtained, and the fluctuation of the threshold voltages of the fieldeffect transistors can be prevented. As a result, electricalcharacteristics of the semiconductor device including the plurality offield effect transistors can be prevented from deteriorating.

The foregoing and other objects, features, aspects and advantages of thepresent invention will become more apparent from the following detaileddescription of the present invention when taken in conjunction with theaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross sectional view showing a 2-power supply semiconductordevice including a plurality of field effect transistors according to afirst embodiment of the invention;

FIGS. 2 to 10 are cross sectional views for use in illustration of thefirst to ninth steps in the process of manufacturing the 2-power supplysemiconductor device including the plurality of field effect transistorsaccording to the first embodiment shown in FIG. 1;

FIG. 11 is a cross sectional view showing a 2-power supply semiconductordevice including a plurality of field effect transistors according to asecond embodiment of the invention;

FIGS. 12 to 21 are cross sectional views for use in illustration of thefirst to tenth steps in the process of manufacturing the 2-power supplysemiconductor device including the plurality of field effect transistorsaccording to the second embodiment shown in FIG. 11;

FIG. 22 is a cross sectional view showing a 2-power supply semiconductordevice including a plurality of field effect transistors according to athird embodiment of the invention;

FIG. 23 is a cross sectional view showing a first variation of the2-power supply semiconductor device including the plurality of fieldeffect transistors according to the third embodiment;

FIG. 24 is a cross sectional view showing a second variation of the2-power supply semiconductor device including the plurality of fieldeffect transistors according to the third embodiment;

FIGS. 25 to 32 are cross sectional views showing the first to eighthsteps in the process of manufacturing the 2-power supply semiconductordevice including the plurality of field effect transistors according tothe third embodiment shown in FIG. 22;

FIG. 33 is a cross sectional view showing a 2-power supply semiconductordevice including a plurality of field effect transistors according to afourth embodiment of the invention;

FIGS. 34 to 37 are cross sectional views for use in illustration of thefirst to fourth steps in the process of manufacturing the 2-power supplysemiconductor device including the plurality of field effect transistorsaccording to the fourth embodiment shown in FIG. 33;

FIGS. 38 to 41 are cross sectional views for use in illustration of aprocess of manufacturing a 2-power supply semiconductor device includinga plurality of field effect transistor according to a first variation ofthe fourth embodiment;

FIGS. 42 and 43 are cross sectional views for use in illustration of thefirst and second steps in a process of manufacturing a 2-power supplysemiconductor device including a plurality of field effect transistorsaccording to a second variation of the fourth embodiment;

FIG. 44 is a cross sectional view showing a 2-power supply semiconductordevice including a plurality of field effect transistors according to athird variation of the fourth embodiment;

FIGS. 45 and 46 are cross sectional views for use in illustration of thefirst and second steps in the process of manufacturing the 2-powersupply semiconductor device including the plurality of field effecttransistors according to the third variation of the fourth embodimentshown in FIG. 44;

FIG. 47 is a cross sectional view showing a 2-power supply semiconductordevice including a plurality of field effect transistors according to afifth embodiment of the invention;

FIG. 48 is a cross sectional view for use in illustration of the firststep in the process of manufacturing the 2-power supply semiconductordevice including the plurality of field effect transistors according tothe fifth embodiment shown in FIG. 47;

FIG. 49 is a cross sectional view showing a 2-power supply semiconductordevice including a plurality of field effect transistors according to asixth embodiment of the invention;

FIGS. 50 to 55 are cross sectional views for use in illustration of thefirst to sixth steps in the process of manufacturing the 2-power supplysemiconductor device including the plurality of field effect transistorsaccording to the sixth embodiment shown in FIG. 49;

FIG. 56 is a cross sectional view showing a 2-power supply semiconductordevice including a plurality of field effect transistors according to aseventh embodiment of the invention;

FIGS. 57 to 60 are cross sectional views for use in illustration of thefirst to fourth steps in the process of manufacturing the 2-power supplysemiconductor device including the plurality of field effect transistorsaccording to the seventh embodiment shown in FIG. 56;

FIG. 61 is a cross sectional view showing a 2-power supply semiconductordevice including a plurality of field effect transistors according to afirst variation of the seventh embodiment;

FIG. 62 is a view schematically showing how an isotropic etching agentruns along grain boundaries inside a doped polysilicon film 32 to reacha second gate insulating film 4, when doped polysilicon film 32 shown inFIG. 56 is isotropically etched;

FIG. 63 is a view schematically showing that an isotropic etching agentdoes not reach a second gate insulating film 4 because of the absence ofgrain boundaries in a silicon film 34, when a silicon film 34 having anamorphous structure as shown in FIG. 61 has its surface isotropicallyetched in the process of manufacture;

FIG. 64 is a cross sectional view showing a 2-power supply semiconductordevice including a plurality of field effect transistors according to asecond variation of the seventh embodiment;

FIGS. 65 to 70 are cross sectional views for use in illustration of thefirst to sixth steps in the process of manufacturing the 2-power supplysemiconductor device including the plurality of field effect transistorsaccording to the second variation of the seventh embodiment shown inFIG. 64;

FIG. 71 is a cross sectional view showing a 2-power supply semiconductordevice including a plurality of field effect transistors according to aneighth embodiment of the invention;

FIG. 72 is a cross sectional view for use in illustration of the firststep in the process of manufacturing the 2-power supply semiconductordevice including the plurality of field effect transistors according tothe eighth embodiment shown in FIG. 71;

FIG. 73 is a cross sectional view showing a 2-power supply semiconductordevice including a plurality of field effect transistors according to aninth embodiment of the invention;

FIGS. 74 to 78 are cross sectional views for use in illustration of thefirst to fifth steps in the process of manufacturing the 2-power supplysemiconductor device including the plurality of field effect transistorsaccording to the ninth embodiment shown in FIG. 73;

FIG. 79 is a cross sectional view showing a conventional 2-power supplysemiconductor device including a plurality of field effect transistors;

FIGS. 80 to 86 are cross sectional views for use in illustration of thefirst to seventh steps in the process of manufacturing the conventional2-power supply semiconductor device including the plurality of fieldeffect transistors shown in FIG. 79;

FIGS. 87 to 93 are cross sectional views for use in illustration of thefirst to seventh steps in the process of manufacturing anotherconventional 2-power supply semiconductor device including a pluralityof field effect transistors; and

FIG. 94 is an enlarged view of region 100 in FIG. 90.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Embodiments of the invention will be now described in conjunction withthe accompanying drawings.

First Embodiment

Referring to FIG. 1, in a 2-power supply semiconductor device includinga plurality of field transistors according to a first embodiment of theinvention, there are formed, on a main surface of a p type semiconductorsubstrate 1, a first field effect transistor supplied with a first powersupply voltage (low Vdd) and a second field effect transistor suppliedwith a second voltage (high Vdd) higher than the first power supplyvoltage, spaced apart from each other. An isolation oxide film 2 isformed between the first and second field effect transistors.

In the low Vdd region, there are formed, on the main surface ofsubstrate 1, a pair of first source/drain regions 10, and a pair of lowconcentration, impurity diffusion regions 8 adjacent thereto, spacedapart from each other and having a first channel region therebetween.Low concentration, n type impurity diffusion region 8 formed adjacent tothe first channel region and high concentration, n type impuritydiffusion region 10 formed adjacent to n type impurity region 8constitute an LDD structure. A first gate insulating film 6 is formed onthe first channel region. A first gate electrode 18 is formed on firstinsulating film 6. A sidewall oxide film 9 is formed on a side of firstgate electrode 18. First source/drain regions 10, low concentrationimpurity diffusion regions 8 adjacent thereto, first gate insulatingfilm 6, and first gate electrode 18 form the first field effecttransistor.

In the high Vdd region, there are formed, on the main surface ofsemiconductor substrate 1, a pair of second source/drain regions 17 anda pair of low concentration impurity diffusion regions 16 adjacentthereto, spaced apart from each other and having a second channeltherebetween. Low concentration, n type impurity diffusion region 16formed adjacent to the second channel region and high concentration, ntype impurity diffusion region 17 formed adjacent to n type impuritydiffusion region 16 constitute an LDD structure. A second gateinsulating film 4 is formed on the second channel region. A second gateelectrode 19 is formed on the second gate insulating film. On a side ofsecond gate electrode 19, a sidewall nitride film 21 formed of a siliconnitride film which serves as an oxidation protection film to preventsecond gate electrode 19 from being oxidized is formed. On a side ofsidewall nitride film 21, a sidewall oxide film 20 is formed. Secondsource/drain regions 17, low concentration impurity diffusion regions 16adjacent thereto, second gate insulating film 4 and second gateelectrode 19 form the second field effect transistor. Herein, thethickness of gate insulating film 4 of the second field effecttransistor supplied with high Vdd should be larger than the thickness ofthe gate insulating film 6 of the first field effect transistor suppliedwith low Vdd.

Thus, sidewall nitride film 21 serving as an oxidation protection filmto prevent second gate electrode 19 from being oxidized is formed on aside of second gate electrode 19, and therefore an oxidizing step toform first gate insulating film 6 in the first field effect transistorcan be performed with sidewall nitride film 21 present on the side ofsecond gate electrode 19. As a result, a lower part of a side of thesecond gate electrode 19 can be prevented from being oxidized, and agate bird's beak can be avoided. As a result, electrical characteristicsof the semiconductor device including the plurality of field effecttransistors can be prevented from deteriorating.

In addition, the sidewall is formed of a silicon nitride film, which hasa higher ability of preventing diffusion of oxygen atoms than a siliconoxide film, can more surely prevent second gate electrode 19 from beingoxidized.

Referring to FIGS. 2 to 10, a process of manufacturing the 2-powersupply semiconductor device including the plurality of field effecttransistors according to the first embodiment of the invention will bedescribed.

As shown in FIG. 2, isolation oxide film 2 is formed on the main surfaceof p type semiconductor substrate 1 to surround an active region. Secondgate insulating film 4 is formed on the active region of the mainsurface of p type semiconductor substrate 1. A first doped polysiliconfilm 3 is formed on second gate insulating film 4 and on isolation oxidefilm 2. A resist pattern 5 a is formed on a region of first dopedpolysilicon film 3 positioned in the high Vdd region to be second gateelectrode 19 (see FIG. 1).

Using resist pattern 5 a as a mask, a part of first doped polysiliconfilm 3 is anisotropically etched away to form second gate electrode 19as shown in FIG. 3, followed by removal of resist pattern 5 a (see FIG.2). A silicon nitride film 11 is formed on second gate insulating film4, second gate electrode 19 and isolation oxide film 2.

Silicon nitride film 11 is anisotropically etched to form, on a side ofsecond gate electrode 19, sidewall nitride film 21 formed of a siliconnitride film which serves as an oxidation protection film to preventsecond gate electrode 19 from being oxidized. A resist pattern 5 b isformed on second gate insulating film 4, second gate electrode 19 andsidewall nitride film 21 to cover the high Vdd region.

Herein, resist pattern 5 b is formed after second gate electrode 19 isformed on second gate insulating film 4, resist pattern 5 b is notdirectly formed on the region—of the surface of second gate insulatingfilm 4 in which second gate electrode 19 is positioned. As a result,during removing resist pattern 5 b, in the region of the surface ofsecond gate insulating film 4, a resist removing processing or a lightetching processing can be prevented. As a result, defects may beprevented from being generated in the region of the surface of secondgate insulating film 4. The condition of the anisotropic etching tosilicon nitride film 11 may be adjusted so that sidewall nitride film 21serving as the oxidation protection film has an arbitrary thickness.Thus, during forming second source/drain regions 17 (see FIG. 1) and lowconcentration impurity diffusion regions 16 (see FIG. 1) in themanufacturing process which will be described, the distance between thesource region and the drain region (the length of the channel region)can be adjusted, and second source/drain regions 17 and lowconcentration impurity diffusion regions 16 having an offset structurecan be readily formed. Thus, a high electric field in the vicinity ofthe boundary region between the channel region, second source/drainregions 17 and low concentration impurity diffusion regions 16 can bereduced. Thus, the generation of electrons with high energy can beprevented. As a result, the fluctuation of the threshold voltage of thesecond field effect transistor caused by introduction of such highenergy electrons into second gate insulating film 14 can be prevented,and as a result electrical characteristics of the semiconductor deviceincluding the plurality of field effect transistors can be preventedfrom deteriorating.

After the step shown in FIG. 4, second gate insulating film 4 present inthe low Vdd region is removed by means of isotropic etching, and thestructure as shown in FIG. 5 results. Thereafter, resist pattern 5 b isremoved.

First gate insulating film 6 is formed on the portion of the mainsurface of p type semiconductor substrate 1 positioned in the low Vddregion, on the surface of second gate insulating film 4, and on secondgate electrode 19 by means of thermal oxidation. Thus, the structure asshown in FIG. 6 results. Herein, the thermal oxidation to form firstgate insulating film 6 can be performed after sidewall nitride film 21serving as the oxidation protection film is formed on the side of secondgate electrode 19. As a result, a lower part of the side of second gateelectrode 19 can be prevented from being oxidized, and a gate bird'sbeak can be avoided. Thus, the threshold voltages of the field effecttransistors can be prevented from increasing. As a result, electricalcharacteristics of the semiconductor device including the plurality offield effect transistors can be prevented from deteriorating.

A second doped polysilicon film 7 is formed to generally cover theentire surface. A resist pattern 5 c is formed on the region of seconddoped polysilicon film 7 to be the first gate electrode 18 (see FIG. 1).As a result, the structure as shown in FIG. 7 results.

Then, using resist pattern 5 c as a mask, a part of second dopedpolysilicon film 7 is anisotropically etched away to form first gateelectrode 18 (see FIG. 1). Herein, silicon oxide film 6 formed by thethermal oxidation during forming first gate insulating film 6 is onsecond gate electrode 19. As a result, during the anisotropic etchingfor forming first gate electrode 18, silicon oxide film 6 serves as astopper, so that damages such as partial removal of second gateelectrode 19 by the anisotropic etching can be prevented. Furthermore,second doped polysilicon film 7 is formed on first gate insulating film6, resist pattern 5 d (see FIG. 8) is not directly formed on first gateinsulating film 64 positioned under first gate electrode in themanufacturing process according to the first embodiment. Therefore, asis the case with second gate insulating film 4, defects caused by aprocessing of removing a resist pattern on the surface of first gateinsulating film 6 can be prevented. Thereafter, resist pattern 5 c (seeFIG. 7) is removed. A resist pattern 5 d (see FIG. 8) is formed to coverthe low Vdd region. Thus, the structure as shown in FIG. 8 results. Atthe time, second doped polysilicon film 7 also remains on a side ofsidewall nitride film 21.

Second doped polysilicon film 7 on the side of sidewall nitride film 21is removed by means of isotropic etching. Thereafter, resist pattern 5 dis removed. An n type impurity is introduced into a prescribed region ofthe main surface of p type semiconductor substrate 1 to form lowconcentration, n type impurity diffusion regions 8 and 16 as shown inFIG. 9. The n type impurity may be phosphorous or arsenic.

Sidewall oxide films 9 and 20 are formed on sides of first gateelectrode 18 and sidewall nitride film 21. First and second gateinsulating films 4 and 6 in the region other than those positioned underfirst and second gate electrodes 18 and 19, sidewall oxide films 9 and20 and sidewall nitride film 21 are etched away. An n type impurity isintroduced into a prescribed region of the main surface of p typesemiconductor substrate 1 to form high concentration, n type impuritydiffusion regions 10 and 17 as shown in FIG. 10.

The 2-power supply semiconductor device according to the firstembodiment is thus manufactured.

Note that in the 2-power supply semiconductor device according to thefirst embodiment, sidewall nitride film 21 serving as the oxidationprotection film is formed on a side of second gate electrode 19, thesame effects can be brought about by forming sidewall nitride film 21serving as the oxidation protection film on a side of first gateelectrode 18.

Second Embodiment

Referring to FIG. 11, in a 2-power supply semiconductor device includinga plurality of field transistors according to a second embodiment of theinvention, there are formed, on a main surface of a p type semiconductorsubstrate 1, a first field effect transistor supplied with a first powersupply voltage (low Vdd) and a second field effect transistor suppliedwith a second voltage (high Vdd) higher than the first power supplyvoltage, spaced apart from each other. An isolation oxide film 2 isformed between the first and second field effect transistors.

In the low Vdd region, there are formed, on the main surface ofsubstrate 1, a pair of first source/drain regions 10 and a pair ofimpurity diffusion regions 26, spaced apart from each other and having afirst channel region therebetween. Intermediate concentration, n typeimpurity diffusion region 26 formed adjacent to the first channel regionand high concentration, n type impurity diffusion region 10 formedadjacent to n type impurity region 26 constitute an LDD structure. Afirst gate insulating film 6 is formed on the first channel region. Afirst gate electrode 18 is formed on first insulating film 6. A sidewalloxide film 9 is formed on a side of first gate electrode 18. Firstsource/drain regions 10, impurity diffusion regions 26, first gateinsulating film 6, and first gate electrode 18 form the first fieldeffect transistor.

In the high Vdd region, there are formed, on the main surface ofsemiconductor substrate 1, a pair of second source/drain regions 17,pairs of impurity diffusion regions 16 and 12 adjacent thereto, spacedapart from each other and having a second channel therebetween. Lowconcentration, n type impurity diffusion region 16 formed adjacent tothe second channel region, intermediate concentration, n type impuritydiffusion region 12 and high concentration, n type impurity-diffusionregion 17 formed adjacent to n type impurity diffusion region 16constitute an LDD structure. A second gate insulating film 4 is formedon the second channel region. A second gate electrode 19 is formed onsecond gate insulating film 4. A sidewall nitride film 21 serving as anoxidation protection film to prevent second gate electrode 19 from beingoxidized is formed on a side of second gate electrode 19. A sidewalloxide film 20 is formed on a side of sidewall nitride film 21. Secondsource/drain regions 17, impurity diffusion regions 16 and 12, secondgate insulating film 4, and second gate electrode 19 form the secondfield effect transistor. Herein, the thickness of the second gateinsulating film 4 of the second field effect transistor supplied withhigh Vdd should be larger than the thickness of the first gateinsulating film 6 of the first field effect transistor supplied with lowVdd.

Thus, with sidewall nitride film 21 serving as the oxidation protectionfilm to prevent the oxidation of second gate electrode 19 being presenton a side of second gate electrode 19, an oxidizing step to form thefirst gate insulating film 6 of first field effect transistor can beperformed in the manufacturing process which will be described. As aresult, as is the case with the first embodiment, a gate bird's beak canbe prevented from being generated in second gate electrode 19. As aresult, electric characteristics of the semiconductor device includingthe plurality of field effect transistors can be prevented fromdeteriorating. Furthermore, the second source/drain regions 17 andimpurity diffusion regions 12 and 16 of the second field effecttransistors which are supplied with high Vdd have a three-region LDDstructure, a high electric field in the boundary region between thesecond channel region and second source/drain regions as well asimpurity diffusion regions 12 and 16 can be more effectively reduced. Asa result, the fluctuation of the threshold voltage of the second fieldeffect transistor can be prevented. As a result, electricalcharacteristics of the semiconductor device including the plurality offield effect transistors can be prevented from deteriorating.

Referring to FIGS. 12 to 21, a method of manufacturing the 2-powersupply semiconductor device including the plurality of field effecttransistors according to the second embodiment will be described.

As shown in FIG. 12, isolation oxide film 2 to surround an active regionis formed on the main surface of p type semiconductor substrate 1.Second gate insulating film 4 is formed on the active region of the mainsurface of semiconductor substrate 1. A first doped polyslicon film 3 isformed on second gate insulating film 4 and isolation oxide film 2. Aresist pattern 5 a is formed on the region of first doped polysiliconfilm 3 positioned in the high Vdd region to be second gate electrode 19(see FIG. 11).

Then, using resist pattern 5 a as a mask, a part of first dopedpolysilicon film 3 is anisotropically etched away to form second gateelectrode 19. Thereafter, resist pattern 5 a is removed. A resistpattern 5 b is formed on second gate insulating film 4 and isolationoxide film 2 positioned in the low Vdd region. An n type impurity isintroduced into a prescribed region of semiconductor substrate 1 to forma low concentration, n type impurity diffusion region 16 as shown inFIG. 13. The n type impurity used is phosphorus, the introduction energyis 20 keV, and the dose is 2×10¹³ cm⁻². The introduction energy may bein the range from 10 to 30 keV. Herein, since second gate electrode 19has been formed on second gate insulating film 4, a resist pattern isnot directly formed in the region of the surface of second gateinsulating film 4 in which second gate electrode 19 is positioned, inthe process of manufacturing which will be described. Defects in theregion of the surface of second gate insulating film 4 which are causedby a processing of removing the resist patterns or a light etchingprocessing can be prevented. Resist pattern 5 b is thereafter removed.

A silicon nitride film 11 is formed on second gate insulating film 4,second gate electrode 19 and isolation oxide film 2. Thus, the structureas shown in FIG. 14 results.

Silicon nitride film 11 is then anisotropically etched to form sidewallnitride film 21 (see FIG. 11) which serves as an oxidation protectionfilm to prevent second gate electrode 19 from being oxidized on asidewall of second gate electrode 19. Resist pattern 5 c (see FIG. 15)is formed on second gate insulating film 4, second gate electrode 19 andsidewall nitride film 21 to cover the high Vdd region to obtain thestructure as shown in FIG. 15.

Then, second gate insulating film 4 present in the low Vdd region isisotropically etched to obtain the structure as shown in FIG. 16. Resistpattern 5 c is then removed away.

First gate insulating film 6 is formed by means of thermal oxidation onthe portion of the main surface of semiconductor substrate 1 positionedin the low Vdd region, on the surface of second gate insulating film 4,and on second gate electrode 19. The structure as shown in FIG. 17 thusresults. Herein, the thermal oxidation to form first gate insulatingfilm 6 may be performed after forming sidewall nitride film 21 servingas the oxidation protection film to prevent second gate electrode 19from being oxidized on a side of second gate electrode 19. As a result,a lower part of a side of second gate electrode 19 can be prevented frombeing oxidized, and a gate bird's beak can be prevented.

A second doped polysilicon film 7 (see FIG. 18) is formed to generallycover the entire surface. A resist pattern 5 d (see FIG. 18) is formedon the region of second doped polysilicon film 7 to be the first gateelectrode (see FIG. 11). Thus, the structure as shown in FIG. 18results.

Then, using resist pattern 5 d as a mask, a part of second dopedpolysilicon film 7 is anisotropically etched away to form first gateelectrode 18 (see FIG. 11). Herein, silicon oxide film 6 formed by thethermal oxidation during forming first gate insulating film 6 is presenton second gate electrode 19. Therefore, during the anisotropic etchingfor forming first gate electrode 18, silicon oxide film 6 serves as astopper, so that damages such as partial removal of second gateelectrode 19 by the anisotropic etching can be prevented. Thereafter,resist pattern 5 d (see FIG. 18) is removed. A resist pattern 5 e (seeFIG. 19) is formed to generally cover the low Vdd region. Thus, thestructure as shown in FIG. 19 results. At the time, second dopedpolysilicon film 7 also remains on a side of sidewall nitride film 21.

Then, second doped polysilicon film 7 on the side of sidewall nitridefilm 21 is isotropically etched away. Then, resist pattern 5 e (see FIG.19) is removed. An n type impurity is introduced into a prescribedregion of the main surface of semiconductor substrate 1, and thusintermediate concentration, n type impurity diffusion regions 26 and 12are formed as shown in FIG. 20. The n type impurity is arsenic, theintroduction energy is 60 keV, and the dose is 2×10¹³ cm⁻². Theintroduction energy may be in the range from 30 to 80 keV.

Sidewall oxide films 9 and 20 (see FIG. 21) are then formed on a side offirst gate electrode 18 and sidewall nitride film 21. First and secondgate insulating films 4 and 6 in the region other than in the regionspositioned under first and second gate electrodes 18 and 19, sidewalloxide films 9 and 20 and sidewall nitride film 21 are etched away. An ntype impurity is introduced into a prescribed region of the main surfaceof semiconductor substrate. As shown in FIG. 21, high concentration, ntype impurity diffusion regions 10 and 17 are formed. Herein, the n typeimpurity is arsenic, the introduction energy is 40 keV, and the dose is5×10¹³ cm⁻². The introduction energy may be in the range from 30 to 60keV.

Thus, the 2-power supply semiconductor device including the plurality offield effect transistors according to the second embodiment ismanufactured.

Third Embodiment

Referring to FIG. 22, in a 2-power supply semiconductor device includinga plurality of field transistors according to a third embodiment of theinvention, there are formed, on a main surface of a p type semiconductorsubstrate 1, a first field effect transistor supplied with a first powersupply voltage (low Vdd) and a second field effect transistor suppliedwith a second voltage (high Vdd) higher than the first power supplyvoltage, spaced apart from each other. An isolation oxide film 2 isformed between the first and second field effect transistors.

In the low Vdd region, there are formed, on the main surface ofsubstrate 1, a pair of first source/drain regions 10, and a pair ofimpurity diffusion regions 8, spaced apart from each other and having afirst channel region. Low concentration, n type impurity diffusionregion 8 formed adjacent to the first channel region and highconcentration, n type impurity diffusion region 10 formed adjacent to ntype impurity region 8 constitute an LDD structure. An oxide nitridefilm 13 serving as a gate insulating film is formed on the first channelregion. A first gate electrode 18 is formed on oxide nitride film 13. Asidewall oxide film 9 is formed on a side of first gate electrode 18.First source/drain regions 10 and impurity diffusion regions 8, oxidenitride film 13, and first gate electrode 18 form the first field effecttransistor.

In the high Vdd region, there are formed, on the main surface ofsemiconductor substrate 1, a pair of second source/drain regions 17, anda pair of impurity diffusion regions 16 spaced apart from each other andhaving a second channel therebetween. Low concentration, n type impuritydiffusion region 16 formed adjacent to the second channel region andhigh concentration, n type impurity diffusion region 17 formed adjacentto n type impurity diffusion region 16 constitute an LDD structure. Asecond gate insulating film 4 is formed on the channel region. A secondgate electrode 19 is formed on second gate insulating film 4. An oxidenitride film 13 is formed on a side of second gate electrode 19 and onsecond gate insulating film 4. A sidewall oxide film 20 is formed onoxide nitride film 13. Second source/drain regions 17, and impuritydiffusion regions 16, second gate insulating film 4, and second gateelectrode 19 form the second field effect transistor. Thus, the gateinsulating film 13 of the first field effect transistor is formed of anoxide nitride film, an end of second gate electrode 19 in the junctionof a lower part of the side of second gate electrode 19 and second gateinsulating film 4 can be prevented from being excessively oxidized. Thegeneration of a gate bird's beak can be restricted. As a result,electrical characteristics of the semiconductor device including theplurality of field effect transistors can be prevented fromdeteriorating. Furthermore, since the first gate insulating film isformed of oxide nitride film 13, the driving capability of thetransistor may be improved in terms of thickness as compared to aconventional silicon oxide film or the like.

Referring to FIG. 23, a first variation of the 2-power supplysemiconductor device including the plurality of field effect transistorsaccording to the third embodiment has basically the same structure asthe 2-power supply semiconductor device according to the firstembodiment shown in FIG. 1. However, in the first variation shown inFIG. 23, the first gate insulating film 13 is formed of oxide nitridefilm. A second variation of the third embodiment shown in FIG. 24 hasbasically the same structure as the device according to the secondembodiment shown in FIG. 11. However, as shown in FIG. 24, in the deviceaccording to the second variation, as is the case with the examplesshown in FIGS. 22 and 23, the first gate insulating film 13 is formed ofoxide nitride film. Therefore, the driving capability of the transistormay be improved as compared to the case of using the conventionalsilicon oxide film in terms of thickness in addition to the effectsbrought about according to the first and second embodiments.

Referring to FIGS. 25 to 32, a process of manufacturing the 2-powersupply semiconductor device including the plurality of field effecttransistors shown in FIG. 22 according to the third embodiment will bedescribed.

The manufacturing process shown in FIG. 25 is identical to themanufacturing process according to the first embodiment shown in FIG. 2.

Now, a part of first doped polysilicon film 3 is anisotropically etchedaway, using a resist pattern 5 a (see FIG. 25) as a mask, to form secondgate electrode 19 (see FIG. 22), followed by removal of resist pattern 5a (see FIG. 25). A resist pattern 5 b (see FIG. 26) is formed on secondgate insulating film 4 and on second gate electrode 19 to cover the highVdd region, and the structure as shown in FIG. 26 results. Herein,resist pattern 5 b is formed after second gate electrode 19 is formed onsecond gate insulating film 4, resist pattern 5 b is not directly formedin the region of the surface of second gate insulating film 4 in whichsecond gate electrode 19 is positioned. As a result, defects in theregion of the surface of second insulating film 4 caused by a processingof removing resist pattern 5 b or a light etching processing can beprevented.

Second gate insulating film 4 present in the low Vdd region isisotropically etched away to obtain the structure as shown in FIG. 27.Thereafter, resist pattern 5 b is removed.

Then, oxide nitride film 13 to be the first gate insulating film isformed at the position of the main surface of semiconductor substrate 1positioned in the low Vdd region, on the surface of second gateinsulating film 4, and on second gate electrode 19 by means of thermaloxidation using N₂O or O₂ as a gas atmosphere. Thus, the structure asshown in FIG. 28 results. Herein, oxide nitride film 13 is formed as thefirst gate insulating film, an end of second gate electrode 19 can beprevented from being excessively oxidized in the junction of a lowerpart of the side of second gate electrode 19 and second gate insulatingfilm 4. Thus, a gate bird's beak can be prevented. Furthermore, sinceoxide nitride film 13 is formed as the first gate insulating film, thethickness of oxide nitride film 13 as the first gate insulating film maybe smaller than a conventional silicon oxide film, while maintaining aprescribed breakdown voltage. As a result, the driving voltage of thefirst field effect transistor can be reduced.

The manufacturing process as shown in FIGS. 29 to 32 is substantiallyidentical to the manufacturing process according to the first embodimentshown in FIGS. 7 to 10.

Thus, the 2-power supply semiconductor device according to the thirdembodiment as shown in FIG. 22 is manufactured.

Fourth Embodiment

Referring to FIG. 33, in a 2-power supply semiconductor device includinga plurality of field transistors according to a fourth embodiment of theinvention, there are formed, on a main surface of a p type semiconductorsubstrate 1, a first field effect transistor supplied with a first powersupply voltage (low Vdd) and a second field effect transistor suppliedwith a second power supply voltage (high Vdd) higher than the firstpower supply voltage, spaced apart from each other. An isolation oxidefilm 2 is formed between the first and second field effect transistors.

In the low Vdd region, there are formed, on the main surface ofsubstrate 1, a pair of first source/drain regions 10, and a pair ofimpurity diffusion regions 8, spaced apart from each other and having afirst channel region therebetween. Low concentration, n type impuritydiffusion region 8 formed adjacent to the first channel region and highconcentration, n type impurity diffusion region 10 formed adjacent to ntype impurity region 8 constitute an LDD structure. A first gateinsulating film 6 is formed on the first channel region. A first gateelectrode 18 is formed on first insulating film 6. A sidewall oxide film9 is formed on a side of first gate electrode 18. First source/drainregions 10, impurity regions 8, first gate insulating film 6, and firstgate electrode 18 form the first field effect transistor.

In the high Vdd region, there are formed, on the main surface ofsemiconductor substrate 1, a pair of second source/drain regions 17 anda pair of impurity diffusion regions 16, spaced apart from each otherand having a second channel therebetween. Low concentration, n typeimpurity diffusion region 16 formed adjacent to the second channelregion and high concentration, n type impurity diffusion region 17formed adjacent to n type impurity diffusion region 16 constitute an LDDstructure. A second gate insulating film 4 is formed on the secondchannel region. A nitrogen doped polysilicon film 14 serving as ananti-oxidation conductive film is formed on second gate insulating film4. A first doped polysilicon film 13 doped with a p type or n typeimpurity is formed on nitrogen doped polysilicon film 14. Nitrogen dopedpolysilicon film 14 and first doped polysilicon film 3 form a secondgate electrode 19. A sidewall oxide film 20 is form on a side of secondgate electrode 19. Second source/drain regions 17, impurity diffusionregions 16, second gate insulating film 4, and second gate electrode 19form the second field effect transistor. Herein, the thickness of secondgate insulating film 4 of the second field effect transistor should belarger than the thickness of the first gate insulating film 6 of thefirst field effect transistor in view of breakdown voltage.

As described above, since nitrogen doped polysilicon film 14 serving asan anti-oxidation conductive film is formed on second gate insulatingfilm 4, it is not necessary to form a resist pattern directly on thesurface of second gate insulating film 4 in the following process ofmanufacturing. Furthermore, before forming second gate electrode 19,first gate insulating film 6 is formed using nitrogen doped polysiliconfilm 14 as a mask, an oxidizing step may be performed while hardlyoxidizing the surface of nitrogen doped polysilicon film 14. As aresult, in the oxidizing step to form a gate insulating film 6, a lowerpart of a side of second gate electrode 19 is not oxidized, and a gatebird's beak can be prevented. Thus, the threshold voltage of the secondfield effect transistor can be prevented from increasing, and electricalcharacteristics of the semiconductor device including the plurality offield effect transistors can be prevented from deteriorating.

In addition, since first and second gate insulating films 6 and 4 areformed in the above-described manner, a conductive layer may be laterformed in the region positioned above first and second gate insulatingfilms 4 and 6, and therefore first and second gate electrodes 18 and 19may be formed in a single patterning processing. As a result, the numberof steps included in the manufacture of the semiconductor device may bereduced.

In addition, nitrogen doped polysilicon film 14 is formed on second gateinsulating film 4, a resist pattern is not directly formed on secondgate insulating film 4. As a result, defects such as localirregularities in the gate insulating film as formed during removing aresist pattern can be avoided. Therefore, the threshold voltages of thefield effect transistors may be prevented from fluctuating. Electricalcharacteristics of the semiconductor device including the plurality offield effect transistors may be prevented from deteriorating.

Referring to FIGS. 34 to 37, a process of manufacturing the 2-powersupply semiconductor device including the plurality of field effecttransistors according to the fourth embodiment will be described.

Isolation oxide film 2 is formed to surround an active region on themain surface of p type semiconductor substrate 1. Second gate insulatingfilm 4 is formed on the active region of the main surface ofsemiconductor substrate 1. Nitrogen doped polysilicon film 14 to be theanti-oxidation conductive film is formed on second gate insulating film4 and isolation oxide film 2. Resist pattern 5 a is formed on nitrogendoped polysilicon film 14 positioned in the high Vdd region. Thus thestructure as shown in FIG. 34 is obtained. Since nitrogen dopedpolysilicon film 14 is formed on second gate insulating film 4 andresist pattern 5 a is formed, resist pattern 5 a is not directly formedon the surface of second gate insulating film. As a result, defectscaused by a processing of removing resist pattern 5 a or a light etchingprocessing can be prevented on the surface of second gate insulatingfilm 4. As a result, the fluctuation of the threshold voltages of thefield effect transistors can be prevented. As a result, electricalcharacteristics of the semiconductor device including the plurality offield effect transistors can be prevented from the deteriorating.

Nitrogen doped polysilicon film 14 and second gate insulating film 4present in the low Vdd region are removed by means of isotropic etching,and the structure as shown in FIG. 35 results. Resist pattern 5 a isthereafter removed.

As shown in FIG. 36, first gate insulating film 6 is formed on the mainsurface of semiconductor substrate 1 positioned in the low Vdd region.At the time, the surface of nitrogen doped polysilicon film 14 is littleoxidized, because its surface had nitrogen introduced.

First doped polysilicon film 3 is formed on first gate insulating film6, nitrogen doped polysilicon film 14 and isolation oxide film 2. Resistpatterns 5 b and 5 c are formed on the regions of first dopedpolysilicon film 3 to be first and second gate electrodes 18 and 19 (seeFIG. 33), and the structure as shown in FIG. 37 results.

Using resist patterns 5 b and 5 c as masks, a part of first dopedpolysilicon film 3 is anisotropically etched away to form first andsecond gate electrodes 18 and 19 (see FIG. 33). Since nitrogen dopedpolysilicon film 14 serving as the anti-oxidation conductive film isformed on second gate insulating film 4, first and second gateelectrodes 18 and 19 may be formed in a single etching processing afterfirst and second gate insulating films 6 and 4 are formed. In addition,since first gate electrode 18 and second gate electrode 19 may be formedin a single anisotropic etching processing, the number of steps includedin the manufacture of the semiconductor device may be reduced.Furthermore, since nitrogen doped polysilicon film 14 is formed onsecond gate insulating film 4, nitrogen doped polysilicon film 14 servesas a barrier against an impurity when the impurity is introduced to formsecond source/drain regions 17 and impurity diffusion regions 16 (seeFIG. 33). As a result, the impurity can be effectively prevented frombeing introduced into the second channel region. As a result, erroneousoperations of the second field effect transistor caused by introductionof the impurity into the second channel region can be more effectivelyprevented.

Thereafter, an impurity is introduced into a prescribed region of themain surface of semiconductor substrate 1, followed by formation ofsidewall oxide films 9 and 20 (see FIG. 33) on sides of first and secondgate electrodes 18 and 19 (see FIG. 33), and the semiconductor device asshown in FIG. 33 is formed.

The 2-power supply semiconductor device including the plurality of fieldeffect transistors according to the fourth embodiment is thusmanufactured.

Referring to FIGS. 38 to 41, a process of manufacturing a 2-power supplysemiconductor device including a plurality of field effect transistorsaccording to a first variation of the fourth embodiment will be nowdescribed.

Isolation oxide film 2 is formed on the main surface of p typesemiconductor substrate 1 to surround an active region. An oxide film(not shown) is formed on the main surface of semiconductor substrate 1.A resist pattern (not shown) is formed on the oxide film positioned inthe low Vdd region. Using the resist pattern as a mask, an impurity isintroduced into the main surface of semiconductor substrate 1 positionedin the high Vdd region. Using the resist pattern as a mask, the oxidefilm positioned in the high Vdd region is isotropically etched away.Thereafter, the resist pattern is removed to form the structure as shownin FIG. 38.

The manufacturing steps shown in FIGS. 39 and 40 are substantiallyidentical to the steps of manufacturing the 2-power supply semiconductordevice including the plurality of field effect transistors according tothe fourth embodiment. However, an oxide film 28 serving as a substrateprotection film is formed on the main surface of semiconductor substratepositioned in the low Vdd region as shown in FIG. 39. Thus, in theoxidizing step to form second gate insulating film 4, the main surfaceof semiconductor substrate 1 positioned in the low Vdd region is notdirectly oxidized. Since oxide film 4 and nitrogen doped polysiliconfilm 14 are formed on oxide film 28, during isotropically etching awaynitrogen doped polysilicon film 14 from the low Vdd region as shown inFIG. 40, oxide film 28 having a sufficient thickness can prevent themain surface of semiconductor substrate 1 positioned in the low Vddregion from being directly damaged by the isotropic etching. Thus, whenfirst gate insulating film 6 (see FIG. 33) is formed in the low Vddregion, the deterioration of the quality of first gate insulating film 6because of possible damages by etching on the main surface ofsemiconductor substrate 1 can be prevented. As a result, the fluctuationof the threshold voltage of the first field effect transistor can beprevented. As a result, electrical characteristics of the semiconductordevice including the plurality of field effect transistors can beprevented from deteriorating.

The manufacturing process according to the first variation of the fourthembodiment shown in FIG. 41 is substantially identical to themanufacturing process according to the fourth embodiment shown in FIG.37. An impurity is thereafter introduced into a prescribed region of themain surface of semiconductor substrate 1, followed by formation ofsidewall oxide films 9 and 20 (see FIG. 33) on sides of first and secondgate electrodes 18 and 19 (see FIG. 33), to form the semiconductordevice as shown in FIG. 33.

Referring to FIGS. 42 and 43, a process of manufacturing a 2-powersupply semiconductor device including a plurality of field effecttransistors according to a second variation of the fourth embodimentwill be now described.

Among the steps of manufacturing the 2-power supply semiconductor deviceincluding the plurality of field effect transistors according to thefourth embodiment, after performing the steps shown in FIGS. 34 and 35,resist pattern 5 a (see FIG. 35) is removed. Then, the entire surface ofsemiconductor substrate 1 is oxidized to form an oxide film 29 on themain surface of semiconductor substrate 1 positioned in the low Vddregion to obtain the structure as shown in FIG. 42.

Then, as shown in FIG. 43, oxide film 29 (see FIG. 42) is isotropicallyetched away. In the manufacturing process according to the secondvariation of the fourth embodiment, after the main surface ofsemiconductor substrate 1 positioned in the low Vdd region is oxidized,oxide film 29 (see FIG. 42) is thus isotropically etched away, possibledamages generated by etching on the main surface positioned in the lowVdd region of semiconductor substrate 1 caused by an etching processingto remove oxide film 4 (see FIG. 34) and nitrogen doped polysilicon film14 (see FIG. 34) from the main surface of semiconductor substrate 1positioned in the low Vdd region can be removed by isotropically etchinga part of the main surface of semiconductor substrate 1 with thedefects. As a result, during forming first gate insulating film 6 (seeFIG. 33), the deterioration of the quality of first gate insulating film6 because of damages by etching such as local irregularities on thesurface of semiconductor substrate 1 may be prevented. As a result, thefluctuation of the threshold voltages of the field effect transistorsmay be prevented, and as a result, electrical characteristics of thesemiconductor device including the plurality of field effect transistorscan be prevented from deteriorating.

After the step shown in FIG. 43, the steps to manufacture the 2-powersupply semiconductor device including the plurality of field effecttransistors according to the fourth embodiment shown in FIGS. 36 and 37are performed to obtain the semiconductor device as shown in FIG. 33.

Referring to FIG. 44, a 2-power supply semiconductor device including aplurality of field effect transistors according to a third variation ofthe fourth embodiment of the invention has substantially the samestructure as the 2-power supply semiconductor device according to thefourth embodiment shown in FIG. 33. However, as shown in FIG. 44, in thedevice according to the third variation, there is formed a dopedpolysilicon film 32 having a conductive impurity between second gateinsulating film 4 and nitrogen doped polysilicon film 14. Therefore, inthe 2-power supply semiconductor device according the third variation,in addition to the effects brought about by the device according to thefourth embodiment, the formation of a depletion layer caused by areduction in the density of the conductive impurity in the vicinity ofsecond gate insulating film 4 when a voltage is supplied to gateelectrode 19 can be restrained. As a result, the fluctuation of thethreshold voltages of the field effect transistors caused by theformation of such a depletion layer can be prevented. Therefore,electrical characteristics of the semiconductor device including theplurality of field effect transistors can be prevented fromdeteriorating.

Referring to FIGS. 45 and 46, a process of manufacturing the 2-powersupply semiconductor device according to the third variation of thefourth embodiment of the invention will be now described.

As shown in FIG. 45, isolation oxide film 2 is formed to surround anactive region on the main surface of p type semiconductor substrate 1.Second gate insulating film 4 is formed on the active region of the mainsurface of semiconductor substrate 1. Doped polysilicon film 32 having aconductive impurity is formed between second gate insulating film 4 andisolation oxide film 2. Nitrogen doped polysilicon film 14 is formed ondoped polysilicon film 32.

After performing the steps substantially identical to the manufacturingsteps according to the fourth embodiment of the invention as shown inFIGS. 34 to 36, a polysilicon film 7 is formed to generally cover theentire semiconductor device as shown in FIG. 46. Resist patterns 5 g and5 h are formed on polysilicon film 7.

Using resist patterns 5 g and 5 h as masks, an anisotropic etching isperformed to partially remove doped polysilicon film 7, nitrogen dopedpolysilicon film 14 and doped polysilicon film 32 to form first andsecond gate electrodes 18 and 19 (see FIG. 44).

Thereafter, an impurity is introduced into a prescribed region of themain surface of semiconductor substrate 1, followed by formation of asidewall oxide film 9 (see FIG. 44) on sides of first and second gateelectrodes 18 and 19 (see FIG. 44), and the semiconductor device asshown in FIG. 44 results.

In the 2-power supply semiconductor device including the plurality offield effect transistors according to the fourth embodiment, nitrogendoped polysilicon film 14 is formed in the high Vdd region, the sameeffects can be brought about by forming nitrogen doped polysilicon film14 in the low Vdd region.

Fifth Embodiment

Referring to FIG. 47, In a 2-power supply semiconductor device includinga plurality of field transistors according to a fifth embodiment of theinvention, there are formed, on a main surface of a p type semiconductorsubstrate 1, a first field effect transistor supplied with a first powersupply voltage (low Vdd) and a second field effect transistor suppliedwith a second voltage (high Vdd) higher than the first power supplyvoltage, spaced apart from each other. An isolation oxide film 2 isformed between the first and second field effect transistors.

In the low Vdd region, there are formed, on the main surface ofsubstrate 1, a pair of first source/drain regions 10, and a pair ofimpurity diffusion regions 8 spaced apart from each other and having afirst channel region therebetween. Low concentration, n type impuritydiffusion region 8 formed adjacent to the first channel region and highconcentration, n type impurity diffusion region 10 formed adjacent to ntype impurity diffusion region 8 constitute an LDD structure. A firstgate insulating film 6 is formed on the first channel region. A firstgate electrode 18 is formed on first insulating film 6. A sidewall oxidefilm 9 is formed on a side of first gate electrode 18. Firstsource/drain regions 10, impurity diffusions 8, first gate insulatingfilm 6, and first gate electrode 18 form the first field effecttransistor.

In the high Vdd region, there are formed, on the main surface ofsemiconductor substrate 1, a pair of second source/drain regions 17, anda pair of impurity diffusion regions 16, spaced apart from each otherand having a second channel therebetween. Low concentration, n typeimpurity diffusion region 16 formed adjacent to the second channelregion and high concentration, n type impurity diffusion region 17formed adjacent to n type impurity diffusion region 16 constitute an LDDstructure. Second gate insulating film 4 is formed on the second channelregion. Doped polysilicon film 32 having a conductive impurity is formedon second gate insulating film 4. A nitride film 27 is formed on a dopedpolysilicon film 32. A doped polysilicon film 7 is formed on nitridefilm 27. Doped polysilicon film 32, nitride film 27 and dopedpolysilicon film 7 form a second gate electrode 19. A sidewall oxidefilm 9 is formed on a side of second gate electrode 19. Herein, nitridefilm 27 is formed by nitriding the surface of doped polysilicon film 32by lamp annealing as in the manufacturing steps which will be describedand is a tunnel insulating film through which a current may be passedwhen voltage is supplied to gate electrode 19. Second source/drainregions 17, impurity diffusion regions 16, second gate insulating film4, and second gate electrode 19 form the second field effect transistor.

Thus, doped polysilicon film 32 and nitride film 27 are formed on secondgate insulating film 4, it is not necessary to form a resist patterndirectly on the surface of second gate insulating film 4. An oxidizingstep to form first gate insulating film 6 may be performed, usingnitride film 27 as a mask before forming second gate electrode 19. As aresult, a lower part of a side of second gate electrode 19 is notoxidized in the step of oxidizing first gate insulating film 6, andtherefore a gate bird's beak can be prevented. Therefore, the thresholdvoltages of the field effect transistors can be prevented fromincreasing. As a result, electrical characteristics of the semiconductordevice including the plurality of field effect transistors can beprevented from deteriorating.

Furthermore, since doped polysilicon film 32 is formed on second gateinsulating film 4, a resist pattern is not formed directly on secondgate insulating film 4. Therefore, as a result, defects such as localirregularities in the gate insulating film as formed during removing theresist pattern can be avoided. Therefore, the threshold voltages of thefield effect transistors may be prevented from fluctuating. Electricalcharacteristics of the semiconductor device including the plurality offield effect transistors may be prevented from deteriorating.

In addition, before forming second gate electrode 19, gate insulatingfilms 6 and 4 are formed, first and second gate electrodes 18 and 19 maybe formed in a single patterning processing by forming a conductivelayer on the regions positioned on first and second gate insulatingfilms 4 and 6. As a result, the number of steps included in themanufacture of semiconductor device may be reduced.

Furthermore, since doped polysilicon film 32 including a conductiveimpurity is formed on second gate insulating film 4, when a voltage issupplied to gate electrode 19, the formation of a depletion layer causedby a reduction in the density of the conductive impurity in the vicinityof second gate insulating film 4 may be restricted. As a result, thefluctuation of the threshold voltages of the field effect transistorscaused by the formation of such a depletion layer can be prevented.Therefore, electrical characteristics of the semiconductor deviceincluding the plurality of field effect transistors can be preventedfrom deteriorating.

Referring to FIG. 48, a process of manufacturing the 2-power supplysemiconductor device according to the fifth embodiment will be nowdescribed.

As shown in FIG. 48, isolation oxide film 2 is formed to surround anactive region on the main surface of p type semiconductor substrate 1.Second gate insulating film 4 is formed on the active region on the mainsurface of semiconductor substrate 1. Doped polysilicon film 32including a conductive impurity is formed on second gate insulating film4 and isolation oxide film 2. The surface of doped polysilicon film 32is nitrided by means of lamp annealing to form nitride film 27.

After the step shown in FIG. 48, the steps substantially the same asthose shown in FIGS. 34 to 37 related to the 2-power supplysemiconductor device according to the fourth embodiment are performed.Thus, semiconductor device as shown in FIG. 47 results.

In the step corresponding to the step shown in FIG. 36, dopedpolysilicon film 32 and nitride film 27 are formed on second gateinsulating film 4, a resist pattern does not have to be formed directlyon the surface of second gate insulating film 4. Furthermore, beforeforming second gate electrode 19, an oxidizing step to form first gateinsulating film 6 using nitride film 27 as a mask may be performed.Thus, in the step of oxidizing first gate insulating film 6, a lowerpart of a side of second gate electrode 19 is not oxidized, and as aresult, a gate bird's beak can be prevented. As a result, the thresholdvoltages of the field effect transistors can be prevented fromincreasing. As a result, electrical characteristics of the semiconductordevice including the plurality of field effect transistors can beprevented from deteriorating.

Furthermore, since first and second gate insulating films 6 and 4 may beformed in the above-described manner, in the step corresponding to thestep shown in FIG. 37, doped polysilicon film 7 (see FIG. 47) may beformed in the region positioned above first and second gate insulatingfilms 6 and 4, and first and second gate electrodes 18 and 19 may beformed in a single patterning processing. As a result, the number ofsteps included in the manufacture of the semiconductor device may bereduced.

Sixth Embodiment

Referring to FIG. 49, in a 2-power supply semiconductor device includinga plurality of field transistors according to a sixth embodiment of theinvention, there are formed, on a main surface of a p type semiconductorsubstrate 1, a first field effect transistor supplied with a first powersupply voltage (low Vdd) and a second field effect transistor suppliedwith a second voltage (high Vdd) higher than the first power supplyvoltage, spaced apart from each other. An isolation oxide film 2 isformed between the first and second field effect transistors.

In the low Vdd region, there are formed, on the main surface ofsubstrate 1, a pair of first source/drain regions 10, and a pair ofimpurity diffusion regions 8 spaced apart from each other and having afirst channel region therebetween. Low concentration, n type impuritydiffusion region 8 formed adjacent to the first channel region and highconcentration, n type impurity diffusion region 10 formed adjacent to ntype impurity diffusion region 8 constitute an LDD structure. A firstgate insulating film 6 is formed on the first channel region. A firstgate electrode 18 is formed on first gate insulating film 6. A sidewalloxide film 9 is formed on a side of first gate electrode 18. Firstsource/drain regions 10, impurity diffusion regions 8, first gateinsulating film 6, and first gate electrode 18 form the first fieldeffect transistor.

In the high Vdd region, there are formed, on the main surface ofsemiconductor substrate 1, a pair of second source/drain regions 17, apair of impurity diffusion regions 16 spaced apart from each other andhaving a second channel therebetween. Low concentration, n type impuritydiffusion region 16 formed adjacent to the second channel region andhigh concentration, n type impurity diffusion region 17 formed adjacentto n type impurity diffusion region 16 constitute an LDD structure. Asecond gate insulating film 4 is formed on the second channel region. Afirst doped polysilicon film 3 is formed on second gate insulating film4. An insulating film 6 of the same material as that of first gateinsulating film 6 is formed on first doped polysilicon film 3. A seconddoped polysilicon film 22 is formed on insulating film 6. First dopedpolysilicon film 3, insulating film 6, and second doped polysilicon film22 form second gate electrode 19. A sidewall oxide film 20 is formed ona side of second gate electrode 19. Second source/drain regions 17,impurity diffusion regions 16, second gate insulating film 4, and secondgate electrode 19 form the second field effect transistor.

Thus, second gate electrode 19 is formed to have first doped polysilicon3, insulating film 6 in the high Vdd region and second doped polysiliconfilm 22, a resist pattern is not directly formed on the surface ofsecond gate insulating film 4 in the step of manufacture which will bedescribed, an oxidizing step to form first gate insulating film 6 in thelow Vdd region may be performed before forming second electrode 19. As aresult, a gate bird's beak caused by oxidation of a side of secondelectrode 19 can be prevented. Furthermore, when high Vdd is supplied tosecond gate electrode 19, a voltage imposed on second gate insulatingfilm 4 can be reduced by a voltage drop at insulating film 6 in the highVdd region.

Assuming that the thickness of first gate insulating film 6 in low Vddregion is t₁, the thickness of second gate insulating film 4 t₂, thethickness of insulating film 6 in the high Vdd region t₃, a voltagesupplied to first gate electrode 18 V₁, and a voltage supplied to secondgate electrode 19 V₂, the thicknesses of insulating film 6 in the highVdd region, first gate insulating film 6 in the low Vdd region andsecond gate insulating film 4 may be adjusted such that t₁/(t₂+t₃) issubstantially equal to V₁/V₂, and the static characteristic of first andsecond field effect transistors can be adjusted to be substantiallyequal to each other.

Referring to FIGS. 50 to 55, a process of manufacturing the 2-powersupply semiconductor device according to the fifth embodiment will benow described.

As shown in FIG. 50, isolation oxide film 2 is formed on the mainsurface of p type semiconductor substrate 1 to surround an activeregion. Second gate insulating film 4 is formed on the active region ofthe main surface of semiconductor substrate 1. First doped polysiliconfilm 3 is formed on second gate insulating film 4 and isolation oxidefilm 2. Thereafter, a resist pattern 5 a is formed on first dopedpolysilicon film 3 positioned in the high Vdd region.

First doped polysilicon film 3 and second gate insulating film 4 presentin the low Vdd region are removed by isotropic etching. Thereafter,resist pattern 5 a is removed. Thus, the structure as shown in FIG. 51results.

First gate insulating film 6 is formed on the portion of the mainsurface of semiconductor substrate 1 positioned in the low Vdd regionand on first doped polysilicon film 3 by means of thermal oxidation.Thus, the structure as shown in FIG. 52 results. Before forming secondgate electrode 19 (see FIG. 49), an oxidizing step to form first gateinsulating film 6 is performed, a gate bird's beak caused by oxidationof a side of second gate electrode 19 can be prevented. Furthermore,since first doped polysilicon film 3 is formed on second gate insulatingfilm 4, a resist pattern is not directly formed onto the surface ofsecond gate insulating film 4. As a result, a processing of removing theresist pattern is not directly performed on the surface of second gateinsulating film 4, and defects on the surface of second gate insulatingfilm 4 can be prevented.

Then, second doped polysilicon film 7 is formed on first gate insulatingfilm 6 and isolation oxide film 2. By forming resist patterns 5 b and 5c on the portion of second doped polysilicon film 7 in the low Vddregion and on the region to be second gate electrode 19 (see FIG. 49),the structure as shown in FIG. 53 results.

Then, using resist patterns 5 b and 5 c as masks, anisotropic etching isperformed to remove part of second doped polysilicon film 7, first gateinsulating film 6, and first doped polysilicon 3 to form second gateelectrode 19 (see FIG. 49). Thereafter, resist patterns 5 b and 5 c (seeFIG. 53) are removed. Resist patterns 5 d and 5 e are formed on secondinsulating film 4, second gate electrode 19, and the region to be thegate electrode 18 of doped polysilicon film 7 (see FIG. 49). Thus, thestructure as shown in FIG. 54 results.

Then, using resist patterns 5 d and 5 e as masks, anisotropic etching isperformed to partially remove second doped polysilicon film 7 and thusfirst gate electrode 18 (see FIG. 49) is formed. Thereafter, resistpatterns 5 d and 5 e are removed to obtain the structure as shown inFIG. 55. Then, an impurity is introduced into a prescribed region of themain surface of semiconductor substrate 1, followed by formation ofsidewall oxide films 9 and 20 (see FIG. 49) on sides of first and secondgate electrodes 18 and 19, to form the semiconductor device as shown inFIG. 49.

Seventh Embodiment

Referring to FIG. 56, in a 2-power supply semiconductor device includinga plurality of field transistors according to a seventh embodiment ofthe invention, there are formed, on a main surface of a p typesemiconductor substrate 1, a first field effect transistor supplied witha first power supply voltage (low Vdd) and a second field effecttransistor supplied with a second voltage (high Vdd) higher than thefirst power supply voltage, spaced apart from each other. An isolationoxide film 2 is formed between the first and second field effecttransistors.

In the low Vdd region, there are formed, on the main surface ofsubstrate 1, a pair of first source/drain regions 10 and a pair ofimpurity diffusion regions 8, spaced apart from each other and having afirst channel region therebetween. Low concentration, n type impuritydiffusion region 8 formed adjacent to the first channel region and highconcentration, n type impurity diffusion region 10 formed adjacent to ntype impurity region 8 constitute an LDD structure. A first gateinsulating film 6 is formed on the first channel region. A dopedpolysilicon film 31 is formed on first gate insulating film 6. Dopedpolysilicon film 31 has a relatively small thickness for example ofabout 500 Å. A natural oxide film 30 is formed on doped polysilicon film31. A doped polysilicon film 7 is formed on natural oxide film 30. Dopedpolysilicon film 31, natural oxide film 30 and doped polysilicon film 7form first gate electrode 18. A sidewall oxide film 9 is formed on aside of first gate electrode 18. First source/drain regions 10 andimpurity diffusion regions 8, first gate insulating film 6 and firstgate electrode 18 form first field effect transistor.

In the high Vdd region, there are formed, on the main surface ofsemiconductor substrate 1, a pair of second source/drain regions 17, apair of impurity diffusion regions 16, spaced apart from each other andhaving a second channel therebetween. Low concentration, n type impuritydiffusion region 16 formed adjacent to the second channel region andhigh concentration, n type impurity diffusion region 17 formed adjacentto n type impurity diffusion region 16 constitute an LDD structure. Asecond gate insulating film 4 is formed on the second channel region. Adoped polysilicon film 32 is formed on second gate insulating film 4.Doped polysilicon film 32 has a relatively small thickness for exampleof about 500 Å. Natural oxide film 30 is formed on doped polysiliconfilm 32. Doped polysilicon film 7 is formed on natural oxide film 30.Doped polysilicon film 32, natural oxide film 30 and doped polysiliconfilm 7 constitute second gate electrode 19. A sidewall oxide film 9 isformed on a side of second gate electrode 19. Second source/drainregions 17, impurity diffusion regions 16, second gate insulating film4, and second gate electrode 19 form the second field effect transistor.

Thus, doped polysilicon films 31 and 32 are formed on first and secondgate insulating films 6 and 4, it is not necessary to form a resistpattern directly on the surfaces of first and second gate insulatingfilms 6 and 4 in the following manufacturing steps. Furthermore, anoxidizing step to form first gate insulating film 6 can be performedusing doped polysilicon film 32 as a mask, before forming second gateelectrode 19. Thus, in the step of oxidizing gate insulating film 6, asa result, a lower part of a side of second gate electrode 19 can beprevented from being oxidized, and a gate bird's beak can be avoided.Thus, the threshold voltages of the field effect transistors can beprevented from increasing. As a result, electrical characteristics ofthe semiconductor device including the plurality of field effecttransistors can be prevented from deteriorating.

Furthermore, by making doped polysilicon films 31 and 32 formed on firstand second gate insulating films 6 and 4 substantially equal inthickness, the thicknesses of doped polysilicon films 31 and 32 to beetched away for forming first and second gate electrodes 18 and 19 canbe made substantially equal in the regions to form first and second gateelectrodes 18 and 19. As a result, during etching for forming first andsecond gate electrodes 18 and 19, the amount of etching to form firstgate electrode 18 can be almost the same as the amount of etching toform second gate electrode 19. As a result, the amount of overetching informing first and second gate electrodes 18 and 19 can be reduced.Therefore, damages caused by overetching of semiconductor substrate 1positioned under doped polysilicon films 31 and 32 to be etched away canbe prevented. As a result, electrical characteristics of thesemiconductor device including the plurality of field effect transistorscan be prevented.

Furthermore, since doped polysilicon films 31 and 32 are formed on firstand second gate insulating films 6 and 4, a resist pattern is not formeddirectly on first and second gate insulating films 6 and 4. As a result,defects such as local irregularities in the gate insulating film causedby the step of ashing to remove a resist pattern can be prevented frombeing generated in first and second gate insulating films 6 and 4.

Referring to FIGS. 57 to 60, a method of manufacturing the 2-powersupply semiconductor device according to the seventh embodiment of theinvention will be described.

As shown in FIG. 57, isolation oxide film 2 to surround an active regionis formed on the main surface of p type semiconductor substrate 1.Second gate insulating film 4 is formed on the active region of the mainsurface of semiconductor substrate 1. Doped polysilicon film 32 isformed on second gate insulating film 4 and isolation oxide film 2.Thereafter, a resist pattern 5 f is then formed on doped polysiliconfilm 32 positioned in the high Vdd region.

Using resist pattern 5 f as a mask, second gate insulating film 4 anddoped polysilicon film 32 positioned in the low Vdd region are etchedaway, followed by removal of resist pattern 5 f. Since doped polysiliconfilm 32 is formed on second gate insulating film 4, resist pattern 5 fis not directly formed on second gate insulating film 4. As a result,defects such as fine irregularities in the surface of second gateinsulating film 4 caused by the removal of resist pattern 5 f can beprevented.

As shown in FIG. 58, first gate insulating film 6 is formed on the mainsurface of semiconductor substrate 1 positioned in the low Vdd regionand on doped polysilicon film 32. Doped polysilicon film 31 is thenformed on first gate insulating film and isolation oxide film 2. Aresist pattern 5 i is formed on doped polysilicon film 31 in the low Vddregion.

Since doped polysilicon film 32 is formed on second gate insulating film4, an oxidizing step to form first gate insulating film 6 can beperformed using doped polysilicon film 32 as a mask before formingsecond gate electrode 19 (see FIG. 56). Thus, in the step of oxidizinggate insulating film 6, a lower part of a side of second gate electrode19 can be prevented from being oxidized, and a gate bird's beak can beavoided. Thus, the threshold voltages of the field effect transistorscan be prevented from increasing. As a result, electricalcharacteristics of the semiconductor device including the plurality offield effect transistors can be prevented from deteriorating.

Furthermore, by making doped polysilicon films 31 and 32 substantiallyequal in thickness, in the step of etching to form first and secondelectrodes 18 and 19 (see FIG. 56), the amount of etching to form firstgate electrode 18 can be substantially the same as the amount of etchingto form second gate electrode 19. As a result, the amount of overetchingduring forming first and second gate electrodes 18 and 19 can bereduced.

Then, doped polysilicon film 31 and gate insulating film 6 positioned inthe high Vdd region are etched away, using resist pattern 5 i as a mask,followed by removal of resist pattern 5 i. Thus, the structure as shownin FIG. 59 results. Herein, polysilicon films 31 and 32 are laid outsuch that the films do not overlap on the main surface of semiconductorsubstrate 1 and isolation oxide film 2. Thus, in the manufacture of thesemiconductor device, there is no such region having a thickness aslarge as the sum of the thicknesses of doped polysilicon films 31 and 32to be etched away. As a result, the doped polysilicon film will not havea locally thick region, the etching margin during etching to form gateelectrodes 18 and 19 can be improved.

A part of the surfaces of first and second doped polysilicon films 31and 32 is isotropically etched away. A doped polysilicon film 7 havingfor example a thickness of about 1500 Å is formed on the entire surfaceof semiconductor substrate 1. At the time, natural oxide film 30 hasbeen formed on the surfaces of doped polysilicon films 31 and 32. Resistpatterns 5 g and 5 h are then formed on doped polysilicon film 7. Thus,the structure as shown in FIG. 60 results.

Thereafter, using resist patterns 5 g and 5 h as masks, part of dopedpolysilicon films 7, 31 and 32, and natural oxide film 30 is etched awayto form first and second gate electrodes 18 and 19 (see FIG. 56). Animpurity is introduced into a prescribed region of the main surface ofsemiconductor substrate 1, followed by formation of a sidewall oxidefilm 9 (see FIG. 56) on sides of first and second gate electrodes 18 and19, and the semiconductor device as shown in FIG. 56 results. Herein, ifthe thickness of doped polysilicon films 31 and 32 is for example notless than 100 Å, during etching to form first and second gate electrodes18 and 19, part of doped polysilicon films 31 and 32 having a sufficientthickness will not be removed during removing natural oxide film 30, anddamages by the etching are not caused on first and second gateinsulating films 6 and 4 positioned under doped polysilicon films 31 and32 and in the main surface of semiconductor substrate 1. As a result,during etching to form first and second gate electrodes 18 and 19, theetching process to remove natural oxide film 30 can be readilyperformed, and the etching margin can be improved as compared to thecase of removing natural oxide film 30 by etching the doped polysiliconfilms.

Referring to FIG. 61, a 2-power supply semiconductor device including aplurality of field effect transistors according to a first variation ofthe seventh embodiment has basically the same structure as the 2-powersupply semiconductor device according to the seventh embodiment shown inFIG. 56 with difference being that silicon films 33 and 34 having anamorphous structure are formed on first and second gate insulating films6 and 4. Since silicon films 33 and 34 formed on first and second gateinsulating films 6 and 4 have an amorphous structure, an isotropicetching agent used for isotropically etching silicon films 33 and 34does not run inside silicon films 33 and 34 to reach first and secondgate insulating films 6 and 4. This is in contrast to the case ofpolysilicon film 32 having a large number of crystals as shown in FIG.62 where the isotropic etching agent runs along grain boundaries toreach gate insulating film 4. Meanwhile, as shown in FIG. 63, in thecase of silicon film 34, having an amorphous structure which is freefrom grain boundaries, the isotropic etching agent does not run alonggrain boundaries to reach gate insulating film 4.

Therefore, damages caused by the isotropic etching agent can beprevented in gate insulating films 4, and the fluctuation of thethreshold voltages of field effect transistors caused by such damages inthe gate insulating film can be prevented. As a result, electricalcharacteristics of the 2-power supply semiconductor device including theplurality of field effect transistors can be prevented fromdeteriorating.

Referring to FIG. 64, a 2-power supply semiconductor device including aplurality of field effect transistors according to a second variation ofthe seventh embodiment has basically the same structure as the 2-powersupply semiconductor device according to the seventh embodiment shown inFIG. 56, with different being that the first gate electrode 31 a isformed only of doped polysilicon film as shown in FIG. 64, and that thesecond gate electrode 32 a is formed only of doped polysilicon film.Since the first and second gate electrodes 31 a and 32 a are formed ofdoped polysilicon films, respectively, the method of forming dopedpolysilicon film 7 (see FIG. 56) in the 2-power supply semiconductordevice according to the seventh embodiment can be omitted. Thus, themanufacturing process can be simplified as compared to the 2-powersupply semiconductor device according to the seventh embodiment.

Referring to FIGS. 65 to 70, a method of manufacturing the 2-powersupply semiconductor device according to the second variation of theseventh embodiment will be now described.

As shown in FIG. 65, isolation oxide film 2 is formed to surround anactive region on the main surface of p type semiconductor substrate.Second gate insulating film 4 is formed on the active region of the mainsurface of semiconductor substrate 1. Doped polysilicon film 32 isformed on second gate insulating film 4 and isolation oxide film 2. Aresist pattern 5 f is formed on doped polysilicon film 32 positioned inthe high Vdd region.

Using resist pattern 5 f as a mask, part of doped polysilicon film 32and second gate insulating film 4 is removed, followed by removal ofresist pattern 5 f. The structure as shown in FIG. 66 thus results.Herein, the thickness of doped polysilicon film 32 has such a thicknessto be used as a gate electrode.

First gate insulating film 6 (see FIG. 67) is formed on the main surfaceof semiconductor substrate 1 and on doped polysilicon film 32. Dopedpolysilicon film 31 (see FIG. 67) is formed on first gate insulatingfilm 6. A resist pattern 5 j (see FIG. 67) is formed in the portionpositioned in the low Vdd region on doped polysilicon film 31. Thus, thestructure as shown in FIG. 67 results.

Since doped polysilicon film 32 is formed on second gate insulating film4, an oxidizing step to form first gate insulating film 6 may beperformed using doped polysilicon film 32 as a mask before formingsecond gate electrode 32 a (see FIG. 64). Thus, in the step of oxidizinggate insulating film 6, as a result, a lower part of a side of secondgate electrode 32 a can be prevented from being oxidized, and a gatebird's beak can be avoided. Thus, the threshold voltages of the fieldeffect transistors can be prevented from increasing. As a result,electrical characteristics of the semiconductor device including theplurality of field effect transistors can be prevented fromdeteriorating.

Doped polysilicon film 31 and first gate insulating film 6 positioned inthe high Vdd region are etched away, using resist pattern 5 j as a mask,followed by removal of resist pattern 5 j, and the structure as shown inFIG. 68 thus results.

Then, as shown in FIG. 69, resist patterns 5 g and 5 h are formed ondoped polysilicon films 31 and 32.

As shown in FIG. 70, using resist patterns 5 g and 5 h (see FIG. 69) asmasks, part of doped polysilicon films 31 and 32 (see FIG. 69) isanisotropically etched away to form first and second gate electrodes 31a and 32 a. Since first and second gate electrodes 31 a and 32 a areformed only of doped polysilicon films 31 and 32 (see FIG. 69) servingas a protection conductive film, the number of steps for forming thedoped polysilicon films can be reduced as compared to the process ofmanufacturing the 2-power supply semiconductor device according to theseventh embodiment shown in FIGS. 57 to 60.

An impurity is then introduced into a prescribed region of the mainsurface of semiconductor substrate 1 followed by formation of a sidewalloxide film 9 (see FIG. 64) on sides of first and second gate electrodes31 a and 32 a (see FIG. 64), and the semiconductor device as shown inFIG. 64 results.

As an application of the second variation of the fourth embodiment,after oxidizing the main surface of semiconductor substrate 1 positionedin the low Vdd region before forming first gate insulating film 6, apart of the surface is isotropically etched to prevent the quality ofgate insulating film 6 from deteriorating. In addition, as applicationsof the first to third embodiment, doped polysilicon films 31 and 32serving as a protection conductive film to protect the gate insulatingfilms may be formed on first and second gate insulating films 6 and 4 tobring about the same effect as the seventh embodiment.

Eighth Embodiment

Referring to FIG. 71 in a 2-power supply semiconductor device includinga plurality of field effect transistors according to an eighthembodiment of the invention, there are formed, on a main surface of a ptype semiconductor substrate 1, a first field effect transistorssupplied with a first power supply voltage (low Vdd) and a second fieldeffect transistor supplied with a second voltage (high Vdd) higher thanthe first power supply voltage, spaced apart from each other. Anisolation oxide film 2 is formed between the first and second fieldeffect transistors.

In the low Vdd region, there are formed, on the main surface ofsubstrate 1, a pair of first source/drain regions 10, a pair of impuritydiffusion regions 8, spaced apart from each other and having a firstchannel region therebetween. Low concentration, n type impuritydiffusion region 8 formed adjacent to the first channel region and highconcentration n type impurity diffusion region 10 formed adjacent to ntype impurity diffusion region 8 constitute an LDD structure. A firstgate insulating film 6 is formed on the first channel region. A dopedpolysilicon film 31 is formed on first gate insulating film 6. A nitridefilm 27 is formed on doped polysilicon film 31. A doped polysilicon film7 is formed on nitride film 27. Doped polysilicon films 31 and 7, andnitride film 27 form a first gate electrode 18. A sidewall oxide film 9is formed on a side of first gate electrode 18. The first source/drainregions 10, impurity diffusion regions 8, first gate insulating film 6,and first gate electrode 18 form the first field effect transistor.

In the high Vdd region, there are formed, on the main surface ofsemiconductor substrate 1, a pair of second source/drain regions 17, anda pair of impurity diffusion regions 16, spaced apart from each otherand having a second channel region therebetween. Low concentration, ntype impurity diffusion region 16 formed adjacent to the second channelregion and high concentration, n type impurity diffusion region 17formed adjacent to n type impurity diffusion region 16 constitute an LDDstructure. A second gate insulating film 4 is formed on the secondchannel region. A doped polysilicon film 32 is formed on second gateinsulating film 4. Nitride film 27 is formed on doped polysilicon film32. Doped polysilicon films 7 and 32 and nitride film 27 form secondgate electrode 19. Sidewall oxide film 9 is formed on a side of secondgate electrode 19. Second source/drain regions 17, impurity diffusionregions 16, second gate insulating film 4 and second gate electrode 19form the second field effect transistor.

Since doped polysilicon film 32 is formed on second gate insulating film4, an oxidizing step to form first gate insulating film 6, using dopedpolysilicon film 32 as a mask can be performed before forming secondgate electrode 19. As a result, in the step of oxidizing gate insulatingfilm 6, a lower part of a side of second gate electrode 19 can beprevented from being oxidized, and a gate bird's beak can be avoided.Thus, the threshold voltages of the field effect transistors can beprevented from increasing. As a result, electrical characteristics ofthe semiconductor device including the plurality of field effecttransistors can be prevented from deteriorating.

Furthermore, nitride film 27 is formed on doped polysilicon films 31 and32 serving as a protection conductive film, a natural oxide filmdifficult to control in thickness can be prevented from being formed ondoped polysilicon films 31 and 32. As a result, the fluctuation of thethicknesses of doped polysilicon films 31, 32 and 7 caused by such anatural oxide film can be prevented. As a result, the amount ofoveretching can be reduced in etching to form first and second gateelectrodes 18 and 19. As a result, damages to semiconductor substrate 1positioned under doped polysilicon films 31 and 32 to be etched away,caused by overetching can be prevented.

Referring to FIG. 72, a method of manufacturing the 2-power supplysemiconductor device according to the eighth embodiment of the inventionwill be described.

After performing the steps in the manufacture of the 2-power supplysemiconductor device according to the seventh embodiment shown in FIGS.57 to 59, doped polysilicon films 31 and 32 are nitrided by lampannealing as shown in FIG. 72, and nitride film 27 serving as anoxidation protection film is formed. Herein, doped polysilicon film 32is formed on second gate insulating film 4, and therefore an oxidizingstep to form first gate insulating film 6 can be performed using dopedpolysilicon film 32 as a mask before forming second gate electrode 19.Thus, in the step of oxidizing gate insulating film 6, a lower part of aside of second gate electrode 19 can be prevented from being oxidized,and a gate bird's beak can be avoided. Thus, the threshold voltages ofthe field effect transistors can be prevented from increasing. As aresult, electrical characteristics of the semiconductor device includingthe plurality of field effect transistors can be prevented fromdeteriorating.

Since nitride film 27 is formed on the surfaces of doped polysiliconfilms 31 and 32, a natural oxide film difficult to control in thicknesscan be prevented from being formed on doped polysilicon films 31 and 32.As a result, variations of the thicknesses of doped polysilicon films31, 32 and 7 caused by such a natural oxide film can be prevented. As aresult, the amount of overetching during etching to form first andsecond gate electrodes 18 and 19 can be reduced. As a result, damagescaused by overetching to semiconductor substrate 1 positioned underdoped polysilicon films 31 and 32 to be etched away can be prevented.

As is the case with the 2-power supply semiconductor device according tothe seventh embodiment shown in FIG. 60, doped polysilicon film 7 isformed in the low Vdd region and the high Vdd region. Resist patternsare thereafter formed on doped polysilicon film 7, anisotropic etchingis performed using the resist patterns as a mask to form first andsecond gate electrodes 18 and 19 (see FIG. 71). An impurity isintroduced into the main surface of semiconductor substrate 1, followedby formation of a sidewall oxide film 9 (see FIG. 71) on sides of firstand second gate electrodes 18 and 19, and the semiconductor device asshown in FIG. 71 is thus obtained.

Ninth Embodiment

Referring to FIG. 73, In a 2-power supply semiconductor device includinga plurality of field transistors according to a ninth embodiment of theinvention, there are formed, on a main surface of a p type semiconductorsubstrate 1, a first field effect transistor supplied with a first powersupply voltage (low Vdd) and a second field effect transistor suppliedwith a second voltage (high Vdd) higher than the first power supplyvoltage, spaced apart from each other. An isolation oxide film 2 isformed between the first and second field effect transistors.

In the low Vdd region, there are formed, on the main surface ofsubstrate 1, a pair of first source/drain regions 10, and a pair ofimpurity diffusion regions 8, spaced apart from each other and having afirst channel region therebetween. Low concentration, n type impuritydiffusion region 8 formed adjacent to the first channel region and highconcentration, n type impurity diffusion region 10 formed adjacent to ntype impurity region 8 constitute an LDD structure. A first gateinsulating film 25 is formed on the first channel region. A first gateelectrode 18 is formed on first insulating film 25. A sidewall oxidefilm 9 is formed on a side of first gate electrode 18. Firstsource/drain regions 10, impurity diffusion regions 8, first gateinsulating film 25, and first gate electrode 18 form the first fieldeffect transistor.

In the high Vdd region, there are formed, on the main surface ofsemiconductor substrate 1, a pair of second source/drain regions 17, anda pair of impurity diffusion regions 16, spaced apart from each otherand having a second channel therebetween. Low concentration, n typeimpurity diffusion region 16 formed adjacent to the second channelregion and high concentration, n type impurity diffusion region 17formed adjacent to n type impurity diffusion region 16 constitute an LDDstructure. A second gate insulating film 4 is formed on the secondchannel region. A second gate electrode 19 is formed on second gateinsulating film 4. Sidewall oxide film 9 is formed on a side of secondgate electrode 19. Second source/drain regions 17, impurity diffusionregions 16, second gate insulating film 4 and second gate electrode 19form the second field effect transistor.

Herein, in the 2-power supply semiconductor device according to theninth embodiment, as will be described in connection with the followingmanufacturing steps, among first and second gate insulating films 25 and4 having substantially the same thickness, only a part of first gateinsulating film 25 is isotropically etched to be reduced in thickness.Therefore, first gate insulating film 25 can be formed before formingsecond gate electrode 19. As a result, a lower part of a side of secondgate electrode 19 can be prevented from being oxidized in the step ofoxidizing to form first gate insulating film 25, and a gate bird's beakcaused by the oxidation can be prevented. Therefore, the thresholdvoltages of the field effect transistors can be prevented fromincreasing.

Referring to FIGS. 74 to 78, a method of manufacturing the 2-powersupply semiconductor device according to the ninth embodiment will benow described.

As shown in FIG. 74, isolation oxide film 2 is formed to surround anactive region on the main surface of p type semiconductor substrate 1.Second gate insulating film 4 is formed on the active region of the mainsurface of semiconductor substrate 1. A resist pattern 5 f is formed onsecond gate insulating film 4 and isolation oxide film 2, positioned inthe high Vdd region.

Using resist pattern 5 f as a mask, a part of the surface of second gateinsulating film 4 positioned in the low Vdd region is isotropicallyetched away to form first gate insulating film 25 (see FIG. 75) thinnerthan second gate insulating film 4 positioned in the high Vdd region.First and second gate insulating films 25 and 4 are formed thicker thantheir final thickness when used as the gate insulating films for thefield effect transistors. The difference between second gate insulatingfilm 4 and first gate insulating film 25 in thickness is setsubstantially identical to the final difference in thickness between thefirst and second gate insulating films used in the field effecttransistors. Resist pattern 5 f is then removed to obtain the structureas shown in FIG. 75.

At the time, the surface of second gate insulating film 4 positioned inthe high Vdd region may suffer from defects such as local irregularitiescaused by the process of removing the resist pattern. The surfaces offirst and second gate insulating films 25 and 4 are isotropically etchedto remove the defects formed by the removal of the resist pattern. Thefirst and second gate insulating films 25 and 4 are isotropically etchedto have the thicknesses of the gate insulating films used in the firstand second field effect transistors.

Since first and second gate insulating films 25 and 4 are formed of asingle insulating film, only a single oxidizing step is necessary toform first and second gate insulating films 25 and 4. As a result, ascompared to the conventional case, the number of oxidizing steps can bereduced by one, and the process of manufacturing the semiconductordevice can thus be simplified. Furthermore, the first and second gateinsulating films are formed by means of isotropic etching, possibledefects such as local irregularities caused by the removal of resistpattern 5 f (see FIG. 74) present on the surface of second gateinsulating films 4 can be removed by the isotropic etching process. As aresult, the first and second gate insulating films 25 and 4 will behighly reliable, and the fluctuation of the threshold voltages of thefield effect transistors can be prevented.

As shown in FIG. 76, a doped polysilicon film 3 is then formed on firstand second gate insulating films 25 and 4, and on isolation oxide film2. Resist patterns 5 b and 5 h are formed on doped polysilicon film 3.

Using resist patterns 5 g and 5 h as masks, a part of doped polysiliconfilm 3 is anisotropically etched away to form first and second gateelectrodes 18 and 19 (see FIG. 77), followed by removal of resistpatterns 5 g and 5 h. As shown in FIG. 77, an impurity is thenintroduced into the main surface of semiconductor substrate 1, usingfirst and second gate electrodes 18 and 19 as masks, n type impuritydiffusion regions 8 and 16 are formed on the main surface ofsemiconductor substrate 1.

Herein, the oxidizing step to form first and second gate insulatingfilms 25 and 4 can be performed before forming second gate electrode 19,a lower part of a side of the gate electrode can be prevented from beingoxidized, and a gate bird's beak can be avoided. Thus, the thresholdvoltages of the field effect transistors can be prevented fromincreasing. As a result, electrical characteristics of the semiconductordevice including the plurality of field effect transistors can beprevented from deteriorating.

A sidewall oxide film 9 is then formed on sides of first and second gateelectrodes 18 and 19 as shown in FIG. 78. Using first and second gateelectrodes 18 and 19 and sidewall oxide film 9 as masks, impurity ionsare introduced into the main surface of semiconductor substrate 11 toform high concentration, n type impurity diffusion regions 10 and 17.The semiconductor device as shown in FIG. 73 is thus obtained.

Although the present invention has been described and illustrated indetail, it is clearly understood that the same is by way of illustrationand example only and is not to be taken by way of limitation, the spiritand scope of the present invention being limited only by the terms ofthe appended claims.

1-2. (Cancelled).
 3. A semiconductor device including a plurality offield effect transistors including a first field effect transistor and asecond field effect transistor, said first field effect transistorincluding, a pair of first source/drain regions formed on a main surfaceof a semiconductor substrate, spaced apart from each other and having afirst channel region therebetween, a first gate insulating film formedon said first channel region and having a first thickness, and a firstgate electrode formed on said first gate insulating film, said secondfield effect transistor including, a pair of second source/drain regionsformed on the main surface of said semiconductor substrate, spaced apartfrom each other and having a second channel region therebetween, asecond gate insulating film formed on said second channel region andhaving a second thickness larger than said first thickness, and a secondgate electrode formed on said second gate insulating film, ananti-oxidation conductive film being formed on at least one of saidfirst and second gate insulating films.
 4. The semiconductor device asrecited in claim 3, further comprising a semiconductor film having aconductive impurity and formed at a position between said anti-oxidationconductive film and at least one of said first and second gateinsulating films.
 5. A semiconductor device including a plurality offield effect transistors including a first field effect transistor and asecond field effect transistor, said first field effect transistorincluding, a pair of first source/drain regions formed on a main surfaceof a semiconductor substrate, spaced apart from each other and having achannel region therebetween, a first gate insulating film formed on saidfirst channel region and having a first thickness, and a first gateelectrode formed on said first gate insulating film, said second fieldeffect transistor including, a pair of second source/drain regionsformed on the main surface of said semiconductor substrate, spaced apartfrom each other and having a second channel region therebetween, asecond gate insulating film formed on said second channel region andhaving a second thickness larger than said first thickness, and a secondgate electrode formed on said second gate insulating film, a protectionconductive film being formed on and in contact with at least one of saidfirst and second gate insulating films.
 6. The semiconductor device asrecited in claim 5, further comprising an anti-oxidation insulation filmfor preventing said protection conductive film from being oxidized beingformed on said protection conductive film.
 7. The semiconductor deviceas recited in claim 5, wherein one of said first and second gateelectrodes have said protection conductive film as a first conductivefilm, an insulating film formed on said first conductive film, and asecond conductive film formed on said insulating film.
 8. Thesemiconductor device as recited in claim 5, wherein said protectionconductive film includes first and second protection conductive films,said first protection conductive film is formed on and in contact withsaid first gate insulating film, and said second protection conductivefilm is formed on and in contact with said second gate insulating film,said first protection conductive film and second protection conductivefilm are substantially identical in thickness.
 9. The semiconductordevice as recited in claim 5, wherein said protection conductive film isformed by depositing a film having an amorphous structure.
 10. Thesemiconductor device as recited in claim 5, further comprising ananti-oxidation film formed on and in contact with said protectionconductive film. 11-17. (Cancelled)